Memory, storage system, and method for operating a memory

Patent metadata

Field	Value
Publication number	US-12585403-B2
Application number	US-202318513215-A
Country	US
Kind code	B2
Filing date	Nov 17, 2023
Priority date	Jun 25, 2023
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

This disclosure provides memory, storage system, and operating method for memory. In an implementation, a method comprising: receiving an operation instruction from the controller; mapping a plurality of initial word line identifiers in the operation instruction to a plurality of physical word line identifiers; performing the operation corresponding to the operation instruction on the plurality of first-type memory cell rows through the plurality of first-type word lines indicated by the plurality of physical word line identifiers; wherein, at least one of third-type memory cell rows is distributed between the first memory cell rows and the second memory cell rows in the plurality of first-type memory cell rows, and data stored in the plurality of first-type memory cell rows corresponds to the same parity data.

First claim

What is claimed is:

1 . A memory, comprising:
a memory array, including a plurality of memory cell rows; a plurality of word lines each coupled to a respective one of the plurality of memory cell rows; and a peripheral circuit coupled to the plurality of word lines and is-configured to:
receive an operation instruction from a controller, wherein the operation instruction comprises a plurality of initial word line identifiers;
map each of the plurality of initial word line identifiers to a respective one of a plurality of physical word line identifiers, the plurality of physical word line identifiers indicating a plurality of first-type word lines that are discontinuous; and
perform an operation corresponding to the operation instruction on a plurality of first-type memory cell rows through the plurality of first-type word lines indicated by the plurality of physical word line identifiers,
wherein, at least one of third-type memory cell rows is distributed between first memory cell rows and second memory cell rows in the plurality of first-type memory cell rows, data stored in the plurality of first-type memory cell rows corresponds to first parity data, and data stored in the at least one of third-type memory cell rows corresponds to second parity data different from the first parity data; and
where in the peripheral circuit is further configured to:
identify each of the plurality of initial word line identifiers as a dummy word line identifier; and
obtain a physical word line identifier corresponding to each of the plurality of initial word line identifiers from a stored mapping relation between the dummy word line identifier and the physical word line identifier.

2 . The memory of claim 1 , wherein the mapping relation includes: a mapping relation between a first dummy word line identifier and a first physical word line identifier, and a mapping relation between a second dummy word line identifier and a second physical word line identifier; and wherein two memory cell rows coupled to two word lines indicated by the first dummy word line identifier and the second dummy word line identifier are adjacent, and memory cell rows other than the two memory cell rows are distributed between two memory cell rows coupled to two word lines indicated by the first physical word line identifier and the second physical word line identifier.

3 . The memory of claim 2 , wherein the first dummy word line identifier includes a first dummy word line number, the second dummy word line identifier includes a second dummy word line number, and a difference between the first dummy word line number and the second dummy word line number is one; and wherein
the first physical word line identifier includes a first physical word line number, and the second physical word line identifier includes a second physical word line number, and a difference between the first physical word line number and the second physical word line number is greater than one.

4 . The memory of claim 3 , wherein the first dummy word line number is less than the second dummy word line number; and wherein
the second physical word line number is a sum of the first physical word line number and a reference value, and the reference value is a positive integer.

5 . The memory of claim 1 , wherein at least one of the third-type memory cell rows is distributed between every two adjacent memory cell rows of the plurality of first-type memory cell rows.

6 . The memory of claim 5 , wherein a quantity of the third-type memory cell rows distributed between every two adjacent memory cell rows of the plurality of first-type memory cell rows is a reference quantity.

7 . The memory of claim 1 , wherein the peripheral circuit is configured to:
in response to determining that a word line mapping instruction is received from the controller, perform an operation of mapping the plurality of initial word line identifiers to the plurality of physical word line identifiers.

8 . The memory of claim 7 , wherein the peripheral circuit is further configured to:
in response to determining that the word line mapping instruction is not received from the controller, perform the operation corresponding to the operation instruction on a plurality of second-type memory cell rows through a plurality of second-type word lines indicated by the plurality of initial word line identifiers; wherein, the plurality of second-type memory cell rows include a plurality of continuous memory cell rows in the memory array, and data stored in the plurality of second-type memory cell rows correspond to same parity data.

9 . The memory of claim 1 , wherein the operation instruction includes a write instruction that comprises a plurality of pieces of data to be written correspondingly to the plurality of initial word line identifiers;
the peripheral circuit is configured to:
identify data to be written corresponding to each of the initial word line identifiers as data to be written corresponding to a respective physical word line identifier; and
perform a program operation on the plurality of first-type memory cell rows through the plurality of first-type word lines, to store the plurality of pieces of data to be written to the plurality of first-type memory cell rows.

10 . The memory of claim 1 , wherein the operation instruction comprises a read instruction;
the peripheral circuit is configured to:
perform a read operation on the plurality of first-type memory cell rows through the plurality of first-type word lines, to obtain data stored in the plurality of first-type memory cell rows.

11 . The memory of claim 10 , wherein the peripheral circuit is further configured to:
in response to determining that data stored in a third memory cell row of the plurality of first-type memory cell rows is erroneous data, determine the initial word line identifier corresponding to the physical word line identifier of the third memory cell row; obtain the first parity data based on the determined initial word line identifier; and correct data stored in the third memory cell row based on the first parity data.

12 . A storage system, comprising:
a memory, configured to:
receive an operation instruction, the operation instruction comprises a plurality of initial word line identifiers;
map the plurality of initial word line identifiers to a plurality of physical word line identifiers, the plurality of physical word line identifiers indicating a plurality of first-type word lines that are discontinuous; and
perform an operation corresponding to the operation instruction on a plurality of first-type memory cell rows through the plurality of first-type word lines indicated by the plurality of physical word line identifiers; and
a controller coupled to the memory and configured to control the memory and send the operation instruction to the memory, wherein, at least one of third-type memory cell rows is distributed between first memory cell rows and send memory cell rows in the plurality of first-type memory cell rows, data stored in the plurality of first-type memory cell rows corresponds to first parity data, and data stored in the at least one of third-type memory cell rows corresponds to second parity data different from the first parity data, wherein the controller coupled to the memory is further configured to:
identify each of the plurality of initial word line identifiers as a dummy word line identifier by sending a word line mapping instruction to the memory; and
wherein the memory is further configured to:
obtain a physical word line identifier corresponding to each of the plurality of initial word line identifiers from a stored m

Assignees

• Yangtze Memory Tech Co Ltd

Inventors

• Ma Lingling
• Guo Lu

Classifications

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0638

  Organizing or formatting or addressing of data · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G11C16/10

  Programming or data input circuits · CPC title