Voltage and current-sensing-less short-circuit protection and localization for power devices

Patent metadata

Field	Value
Publication number	US-12584975-B2
Application number	US-202418440073-A
Country	US
Kind code	B2
Filing date	Feb 13, 2024
Priority date	Feb 28, 2023
Publication date	Mar 24, 2026
Grant date	Mar 24, 2026

Abstract

A short-circuit protection and localization circuit for power devices includes a first subcircuit for detecting dv/dt of a power device at turn on, a second subcircuit for short-circuit fault localization and soft turn-off of the power device, the second subcircuit including a totem-pole driver having an upper switch and a lower switch, and a third subcircuit for detecting short-circuit faults based on the output (V dip ) of the first subcircuit and the output of an upper switch (V p ) of the second subcircuit. The first subcircuit outputs a voltage (V dip ) having a magnitude that is proportional to dv/dt of the power device. The third subcircuit outputs a signal (V sto ) to the second subcircuit that causes the second subcircuit to softly turn-off the power device. The second subcircuit outputs a voltage of the upper switch (V p ) and a fault-latching signal for short-circuit localization.

First claim

What is claimed is:

1 . A circuit for short-circuit protection and localization for power devices, the circuit comprising:
a first subcircuit for detecting dv/dt of a power device at turn on, wherein the first subcircuit outputs a voltage (V dip ) having a magnitude that is proportional to dv/dt of the power device; a second subcircuit for short-circuit fault localization and soft turn-off of the power device, the second subcircuit comprising a totem-pole driver having an upper switch and a lower switch, wherein the second subcircuit outputs a voltage of the upper switch (V p ) and a fault-latching signal for short-circuit localization; and a third subcircuit for detecting short-circuit faults based on the output (V dip ) of the first subcircuit and the output of the upper switch (V p ) of the second subcircuit, wherein the third subcircuit outputs a signal (V sto ) to the second subcircuit that causes the second subcircuit to softly turn-off the power device.

2 . The circuit of claim 1 , wherein the first subcircuit comprises an R-C differential circuit having a capacitor (C sen ) and a resistor (R sen ).

3 . The circuit of claim 2 , wherein the voltage (V dip ) output by the first subcircuit is the voltage across the resistor (R sen ).

4 . The circuit of claim 1 , wherein the second subcircuit comprises two gate resistors (R on , R off ) that control turn-on and turn-off switching speeds, respectively.

5 . The circuit of claim 4 , wherein each of the two gate resistors (R on , R off ) are sized based on desired turn-on and turn-off switching speeds for the power device, respectively.

6 . The circuit of claim 1 , wherein the second subcircuit comprises a soft turn off (STO) MOSFET and a resistor (R sto ), wherein the STO MOSFET and the resistor reduce gate-source voltage of the power device to initiate soft turn off of the power device.

7 . The circuit of claim 1 , wherein the third subcircuit comprises a voltage divider that scales the voltage of the upper switch (V p ) of the second subcircuit.

8 . The circuit of claim 7 , wherein the third subcircuit comprises a buffer to generate a pulse-width modulated signal (V pwm ) from the scaled voltage of the upper switch (V p ).

9 . The circuit of claim 8 , wherein the third subcircuit comprises a rising-edge delay component that delays a rising edge of the pulse-width modulated signal (V pwm ) to generate a delayed pulse-width modulated signal (V pwmd ).

10 . The circuit of claim 9 , wherein the third subcircuit comprises a resistor, a capacitor, and a diode that extract a rising edge of the pulse-width modulated signal (V pwm ).

11 . The circuit of claim 1 , wherein the third subcircuit comprises a voltage divider with a clamping diode followed by an inverted buffer and a one-shot block to generate an engagement signal (V dip,eg ) from the voltage (V dip ) output by the first subcircuit, wherein the engagement signal (V dip,eg ) is a one-shot pulse.

12 . The circuit of claim 1 , wherein the third subcircuit comprises:
a voltage divider that scales the voltage of the upper switch (V p ) of the second subcircuit; a buffer to generate a pulse-width modulated signal (V pwm ) from the scaled voltage of the upper switch (V p ); a resistor, a capacitor, and a diode that extract a rising edge of the pulse-width modulated signal (V pwm ); a voltage divider with a clamping diode followed by an inverted buffer and a one-shot component to generate an engagement signal (V dip,eg ) from the voltage (V dip ) output by the first subcircuit, wherein the engagement signal (V dip,eg ) is a one-shot pulse; and an RS flip-flop which generates a signal (V en ) from the rising edge of the pulse-width modulated signal (V pwm ) and the engagement signal (V dip,eg ).

13 . The circuit of claim 12 , wherein the third subcircuit comprises a rising-edge delay component that delays a rising edge of the pulse-width modulated signal (V pwm ) to generate a delayed pulse-width modulated signal (V pwmd ), wherein the signal (V en ) from the RS flip-flop and the delayed pulse-width modulated signal (V pwmd ) are fed into an AND gate to generate the signal (V sto ) output by the third subcircuit.

14 . The circuit of claim 12 , wherein the RS flip-flop comprises two NOR gates.

15 . The circuit of claim 1 , wherein a pulse width modulated (PWM) signal is provided as an input to the second subcircuit.

16 . The circuit of claim 15 , wherein the pulse width modulated (PWM) signal and the fault-latching signal output by the second subcircuit are fed into a NAND gate, and wherein an output of the NAND gate is provided to both the upper switch and the lower switch of the second subcircuit.

17 . The circuit of claim 1 , wherein the totem-pole driver of the second subcircuit is supplied by a positive and a negative driving voltage (V cc , V ee ).

18 . The circuit of claim 1 , wherein the power device is one of a silicon (Si) MOSFET, a silicon insulated-gate bipolar transistor (Si IGBT), a gallium nitride high-electron-mobility transistor (GaN HEMT), or a silicon carbide (SiC) MOSFET.

19 . The circuit of claim 18 , wherein the first subcircuit is connected between a drain and a source of the power device.

20 . The circuit of claim 1 , wherein the fault-latching signal is output to an external circuit, a controller, or a computing device.

Assignees

• Univ Florida State Res Found Inc

Inventors

• Li Hui
• Guo Zhehui

Classifications

• G01R31/2642

  Testing semiconductor operation lifetime or reliability, e.g. by accelerated life tests · CPC title

• G01R19/0053

  Noise discrimination; Analog sampling; Measuring transients (measuring characteristics of individual pulses G01R29/02; digital sampling G01R19/2509; measuring noise figure G01R29/26) · CPC title

• G01R29/023

  Measuring pulse width · CPC title

• G01R19/12

  Measuring rate of change · CPC title

• G01R31/52 Primary

  Testing for short-circuits, leakage current or ground faults · CPC title