Display substrate, display device, and wiring method

Patent metadata

Field	Value
Publication number	US-12581822-B2
Application number	US-202118275931-A
Country	US
Kind code	B2
Filing date	Oct 22, 2021
Priority date	Feb 22, 2021
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

Provided is a display substrate. The display substrate includes: a display region and a bonding region on a side of the display region, wherein the display region includes a plurality of pixel columns; and a wiring structure, disposed between the display region and the bonding region and including a plurality of traces, wherein one of the plurality of traces corresponds to one of the plurality of pixel columns, the plurality of traces are electrically connected to the plurality of pixel columns to supply an electric signal to pixels, and each of the plurality of traces includes a plurality of sub-traces, wherein at least one of line lengths and line widths of sub-traces corresponding to at least a part of the plurality of traces are different, such that total resistances of the at least the part of the plurality of traces are basically equal.

First claim

The invention claimed is:

1 . A display substrate, comprising:
a display region and a bonding region on a side of the display region, wherein the display region comprises a plurality of pixel columns that are sequentially arranged; and a wiring structure, disposed between the display region and the bonding region and comprising a plurality of traces that are sequentially arranged, wherein one of the plurality of traces corresponds to one of the plurality of pixel columns, the plurality of traces are electrically connected to the plurality of pixel columns to supply an electric signal to pixels in the plurality of pixel columns, and each of the plurality of traces comprises a plurality of sub-traces, wherein at least one of line lengths and line widths of sub-traces corresponding to at least a part of the plurality of traces are different, such that total resistances of the at least the part of the plurality of traces are basically equal; wherein the wiring structure further comprises a first wiring space, a second wiring space, and a third wiring space that are sequentially arranged, wherein the first wiring space is proximal to the display region, and the plurality of sub-traces are arranged in at least one of the first wiring space, the second wiring space, and the third wiring space.

2 . The display substrate according to claim 1 , wherein in the first wiring space, each of the plurality of sub-traces comprises a first adjustment trace with a line length within a unit distance greater than a predetermined length, wherein line lengths of the first adjustment traces are sequentially increased in a direction from a side edge of the display region to a center of the display region.

3 . The display substrate according to claim 1 , wherein the second wiring space comprises a first region and a second region that are disposed proximal to a side edge of the display region and are adjacent to each other; wherein
in the first region, each of the plurality of sub-traces comprises a first adjustment trace, wherein line lengths of the first adjustment traces are sequentially increased in a direction from the side edge of the display region to a center of the display region; and in the second region, each of the plurality of sub-traces comprises a second adjustment trace with a line width greater than a predetermined width, wherein line lengths of the second adjustment traces are sequentially reduced in the direction from the side edge of the display region to the center of the display region.

4 . The display substrate according to claim 1 , wherein the second wiring space comprises a third region, the third region comprising a plurality of sub-regions, wherein in each of the plurality of sub-regions, each of the plurality of sub-traces comprises a first adjustment trace, wherein line lengths of the first adjustment traces are sequentially increased in a direction from a side edge of the display region to a center of the display region.

5 . The display substrate according to claim 4 , wherein the plurality of sub-regions comprise a first sub-region and a second sub-region that are adjacent; wherein
in the first sub-region, the line lengths of the first adjustment traces are sequentially increased from a first line length in the direction from the side edge of the display region to the center of the display region; and in the second sub-region, the line lengths of the first adjustment traces are sequentially increased from a second line length in the direction from the side edge of the display region to the center of the display region, and the second line length is greater than the first line length.

6 . The display substrate according to claim 1 , wherein the third wiring space comprises a fourth region and a fifth region that are adjacent; wherein
sub-traces in the fourth region comprise a second adjustment trace, wherein line lengths of the second adjustment traces are sequentially reduced in a direction from a side edge of the display region to a center of the display region; and sub-traces in the fifth region comprise a first adjustment trace, wherein line lengths of the first adjustment traces are sequentially increased in a direction from the side edge of the display region to the center of the display region.

7 . The display substrate according to claim 1 , wherein the wiring structure comprises a fourth wiring space, the fourth wiring space comprising a sixth region and a seventh region that are adjacent; wherein
sub-traces in the sixth region comprise a second adjustment trace, wherein line lengths of the second adjustment traces are sequentially reduced in a direction from a side edge of the display region to a center of the display region; and sub-traces in the seventh region comprise a first adjustment trace, wherein line lengths of the first adjustment traces are sequentially increased in the direction from the side edge of the display region to the center of the display region.

8 . The display substrate according to claim 1 , wherein the wiring structure further comprises:
a first connection space, wherein the first connection space is disposed between the first wiring space and the second wiring space, and each of the plurality of traces comprises a connection sub-trace in the first connection space; and a second connection space, wherein the second connection space is disposed between the second wiring space and the third wiring space, and each of the plurality of traces comprises a connection sub-trace in the second connection space.

9 . The display substrate according to claim 1 , wherein each of the plurality of sub-traces comprises a first adjustment trace bending and extending in a wiring direction.

10 . The display substrate according to claim 1 , further comprising: a conduction line, wherein the conduction line is configured to be bonded to a flexible circuit board, and comprises a first power signal line and a second power signal line, wherein the first power signal line is configured to supply a first power voltage to the pixels, and the second power signal line is configured to supply a second power voltage to the pixels.

11 . The display substrate according to claim 1 , further comprising: a first conduction layer and a second conduction layer, wherein adjacent traces are respectively disposed in the first conduction layer and the second conduction layer.

12 . The display substrate according to claim 1 , further comprises: a base substrate, wherein the pixel comprises at least one thin-film transistor and storage capacitor; wherein
the at least one thin-film transistor comprises an active layer on the base substrate, a first gate insulation layer on a side, distal from the base substrate, of the active layer, a gate on a side, distal from the base substrate, of the first gate insulation layer, a second gate insulation layer on a side, distal from the base substrate, of the gate, an interlayer insulation layer on a side, distal from the base substrate, of the second gate insulation layer, and a source and drain on a side, distal from the base substrate, of the interlayer insulation layer; and the storage capacitor comprises a first plate and a second plate, wherein the first plate and the gate are disposed on a same layer, and the second plate is disposed between the second gate insulation layer and the interlayer insulation layer.

13 . The display substrate according to claim 12 , wherein at least a part of the plurality of traces and the first plate are disposed on a same layer, and at least a part of the plurality of traces and the second plate are disposed on a same layer, and the at least the part of the

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Qu Yi
• Liao Maoying
• Dai Junxiu
• Bai Lu
• Zhou Yang
• Zhang Xin

Classifications

• H10K59/00

  Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00 · CPC title

• H10K59/1315

  comprising structures specially adapted for lowering the resistance · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title