Display substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-12581815-B2
Application number	US-202218022754-A
Country	US
Kind code	B2
Filing date	Mar 29, 2022
Priority date	Mar 29, 2022
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A display substrate includes a base substrate, a pixel circuit layer, a first planarization layer, at least one transparent conductive layer, and a plurality of first light-emitting elements. The base substrate includes a first display region and a second display region, wherein the first display region at least partially surrounds the second display region. The pixel circuit layer is located in the first display region, and includes a plurality of pixel circuits, wherein the plurality of pixel circuits include a plurality of first pixel circuits. A plurality of first light-emitting elements are located in the second display region. The first planarization layer is located on a side of the pixel circuit layer away from the base substrate, and is located in the first display region and the second display region.

First claim

The invention claimed is:

1 . A display substrate, comprising:
a base substrate including a first display region and a second display region, wherein the second display region is surrounded by at least a part of the first display region; a pixel circuit layer located in the first display region, wherein the pixel circuit layer comprises a plurality of pixel circuits, and the plurality of pixel circuits comprise a plurality of first pixel circuits; a plurality of first light-emitting elements located in the second display region; a first planarization layer located on a side of the pixel circuit layer away from the base substrate, and located in the first display region and the second display region; and at least one transparent conductive layer located on a side of the first planarization layer away from the base substrate, wherein the transparent conductive layer comprises a plurality of first transparent conductive lines and at least one auxiliary structure, and the plurality of first light-emitting elements and the plurality of first pixel circuits are coupled through the plurality of first transparent conductive lines; wherein an orthographic projection of the at least one auxiliary structure on the base substrate is overlapped with an orthographic projection of at least one of the plurality of pixel circuits on the base substrate; wherein the display substrate further comprises a first conductive layer located between the pixel circuit layer and the first planarization layer, the first conductive layer comprises at least one shield electrode electrically connected with at least one of the plurality of pixel circuits, and an orthographic projection of the at least one auxiliary structure on the base substrate is overlapped with an orthographic projection of the shield electrode on the base substrate; and wherein each pixel circuit at least comprises a drive transistor, a threshold compensation transistor and a first reset transistor, and the drive transistor, the threshold compensation transistor and the first reset transistor are all electrically connected to a first node; the first node is a connection point of the first reset transistor, the drive transistor, and the threshold compensation transistor; and the orthographic projection of the shield electrode on the base substrate is arranged to cover an orthographic projection of the first node of the pixel circuit on the base substrate.

2 . The display substrate according to claim 1 , wherein the pixel circuit layer comprises a second conductive layer, and the second conductive layer comprises a first power supply line, and the shield electrode is electrically connected with the first power supply line.

3 . The display substrate according to claim 2 , wherein the at least one auxiliary structure is electrically connected with the shield electrode.

4 . The display substrate according to claim 1 , wherein the orthographic projection of the shielding electrode on the base substrate is an irregular shape.

5 . The display substrate according to claim 2 , wherein the display substrate comprises a second planarization layer, the second planarization layer of the display substrate is provided between the first conductive layer and the second conductive layer, and the first conductive layer is electrically connected to the second conductive layer through a first via hole of the display substrate penetrating the second planarization layer; and an orthographic projection of at least one of the plurality of first transparent conductive lines on the base substrate is overlapped with an orthographic projection of the first via hole on the base substrate.

6 . The display substrate according to claim 1 , wherein the first transparent conductive lines comprise edge transparent conductive lines, and the edge transparent conductive line is adjacent to the at least one auxiliary structure.

7 . The display substrate according to claim 6 , wherein the at least one auxiliary structure is located between two of the edge transparent conductive lines.

8 . The display substrate according to claim 6 , wherein a spacing between the at least one auxiliary structure and an adjacent edge transparent conductive line is greater than or equal to 2 microns and less than or equal to 3 microns.

9 . The display substrate according to claim 1 , wherein the at least one auxiliary structure comprises a plurality of auxiliary blocks arranged regularly.

10 . The display substrate according to claim 9 , wherein the plurality of auxiliary blocks of the at least one auxiliary structure are arranged in an array, and shapes and sizes of the plurality of auxiliary blocks are substantially the same.

11 . The display substrate according to claim 10 , wherein an orthographic projection of each of the plurality of auxiliary blocks on the base substrate is rectangular.

12 . The display substrate according to claim 9 , wherein the plurality of auxiliary blocks of the at least one auxiliary structure are arranged in a ring.

13 . The display substrate according to claim 9 , wherein the pixel circuit layer comprises a second conductive layer, and the second conductive layer comprises a first power supply line, at least one auxiliary block of the at least one auxiliary structure is electrically connected to the first power supply line.

14 . The display substrate according to claim 9 , wherein at least two adjacent auxiliary blocks of the at least one auxiliary structure are connected through one connection line of the display substrate.

15 . The display substrate according to claim 14 , wherein the plurality of auxiliary blocks of the at least one auxiliary structure are divided into a plurality of groups, each group includes at least two auxiliary blocks, and the auxiliary blocks within one group are connected by one connection line of the display substrate or a plurality of connection lines of the display substrate.

16 . The display substrate according to claim 1 , wherein an orthographic projection of the at least one auxiliary structure on the base substrate is ring-shaped or mesh-shaped.

17 . The display substrate according to claim 1 , wherein the plurality of pixel circuits further comprises a plurality of second pixel circuits located in the first display region; the display substrate further comprises a plurality of second light-emitting elements located in the first display region; and at least one second pixel circuit of the plurality of second pixel circuits is electrically connected to at least one second light-emitting element of the plurality of second light-emitting elements, and the at least one second pixel circuit is configured to drive the at least one second light-emitting element.

18 . A display apparatus, comprising a display substrate, wherein the display substrate comprises:
a base substrate including a first display region and a second display region, wherein the second display region is surrounded by at least a part of the first display region; a pixel circuit layer located in the first display region, wherein the pixel circuit layer comprises a plurality of pixel circuits, and the plurality of pixel circuits comprise a plurality of first pixel circuits; a plurality of first light-emitting elements located in the second display region; a first planarization layer located on a side of the pixel circuit layer away from the base substrate, and located in the first display region and the second display region; and at least one transparent conductive layer located on a side of the first planarization lay

Assignees

• Mianyang Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Tang Qing
• Gu Qingsong
• Xiong Lin
• Ma Ning
• Wang Danfeng

Classifications

• G09G2300/0842

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• G09G2300/0426

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• H10K59/124

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