Array substrate, display panel, and display device with compensation signal near hole area

US12581740B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12581740-B2
Application numberUS-202318338592-A
CountryUS
Kind codeB2
Filing dateJun 21, 2023
Priority dateFeb 24, 2021
Publication dateMar 17, 2026
Grant dateMar 17, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An array substrate, a display panel and a display device. The array substrate includes: a hole area and a display area which is partially surrounding the hole area; a plurality of first signal lines located in the display area and including a plurality of first category signal lines and a plurality of second category signal lines; a plurality of first connection signal lines, each of which includes a first connection section, a second connection section and a third connection section that are connected sequentially; and a plurality of first compensation signal lines located in the display area and extending in the second direction, wherein at least a portion of the plurality first compensation signal lines is located on the extension of the first connection signal lines in the second direction.

First claim

Opening claim text (preview).

What is claimed is: 1 . An array substrate including a hole area and a display area which is partially surrounding the hole area, the array substrate comprising: a plurality of first signal lines located in the display area and including a plurality of first category signal lines and a plurality of second category signal lines, wherein each of the first category signal lines extends in a first direction, and each of the second category signal lines comprises a first section and a second section separated by the hole area and extending in the first direction; a plurality of first connection signal lines, at least a portion of which is located in the display area but in a different film layer from the first category signal lines, wherein each of the first connection signal lines comprises a first connection section, a second connection section and a third connection section that are connected sequentially, the second connection section is connected between the first connection section and the third connection section, the first connection section is electrically connected to the first section, the third connection section is electrically connected to the second section, and both the first connection section and the third connection section extend in a second direction; and A plurality of first compensation signal lines located in the display area and extending in the second direction, wherein at least a portion of the plurality of first compensation signal lines is collinear with the first connection section or the third connection section in the second direction. 2 . The array substrate according to claim 1 , wherein an orthogonal projection of the first compensation signal line on a plane where the array substrate is located does not overlap with an orthogonal projection of the first connection section on the plane, or the orthogonal projection of the first compensation signal line on the plane does not overlap with an orthogonal projection of the third connection section on the plane. 3 . The array substrate according to claim 1 , wherein at least a portion of the plurality first compensation signal lines is located between adjacent first connection sections, or at least a portion of the plurality first compensation signal lines is located between adjacent third connection sections. 4 . The array substrate according to claim 1 , wherein at least a portion of the plurality first compensation signal lines is aligned with the first connection section in the second direction, or at least a portion of the plurality first compensation signal lines is aligned with the third connection section in the second direction. 5 . The array substrate according to claim 1 , wherein the plurality of the first compensation signal lines, the first connection sections of the plurality of the first connection signal lines and the third connection sections of the plurality of the first connection signal lines are uniformly distributed in the display area along the first direction. 6 . The array substrate according to claim 1 , further comprising: a plurality of second signal lines located in the display area, wherein at least a portion of the plurality of first compensation signal lines is electrically connected to the second signal line, and the second signal line is a voltage signal line. 7 . The array substrate according to claim 6 , wherein the second signal line is a power signal line; and each of the second signal lines comprises a first sub-signal line and a second sub-signal line which are electrically connected to each other but located in different film layers, wherein at least a portion of the plurality of first compensation signal lines is located in a same film layer as and electrically connected to one of the first sub-signal line and the second sub-signal line. 8 . The array substrate according to claim 7 , wherein the first direction is a column direction, and the second direction is a row direction, the first signal line is a data signal line, and the second signal line extends in the first direction; and wherein the first signal line is located in a same film layer as the first sub-signal line but with a separation distance from the first sub-signal line, and the first compensation signal line and the first connection signal line are located in a same film layer as the second sub-signal line. 9 . The array substrate according to claim 7 , wherein the second sub-signal line comprises a first category sub-signal line and a second category sub-signal line, and the second category sub-signal line comprises a first sub-section and a second sub-section which are separated by the first connection signal line; and at least a portion of the second connection sections extends between the first sub-section and the second sub-section. 10 . The array substrate according to claim 7 , wherein the first compensation signal line comprises a first category compensation signal line and a second category compensation signal line; the first category compensation signal line is located between the first connection signal line and the hole area, and is connected to the first connection signal line; and the second category compensation signal line is separated from the hole area by the first connection signal line, and is connected to the second sub-signal line. 11 . The array substrate according to claim 6 , wherein the first direction is a row direction, the second direction is a column direction, the first signal line is a scanning signal line, a light emission control signal line or a reference voltage signal line, and the second signal line extends in the second direction; and the first signal lines are located in a different film layer from the second signal lines. 12 . The array substrate according to claim 6 , wherein the first direction is a column direction, the second direction is a row direction and the first signal line is a data signal line, and wherein the array substrate further comprises: a plurality of third signal lines which are scanning signal lines, light emission control signal lines or reference voltage signal lines, wherein the third signal lines comprise a plurality of third category signal lines and a plurality of fourth category signal lines, wherein each of the third category signal lines is located in the display area and extends in the second direction, and each of the fourth category signal lines comprises a third section and a fourth section separated by the hole area and extending in the second direction; a plurality of second connection signal lines, at least a portion of which is located in the display area but in a different film layer from the third category signal lines, wherein each of the second connection signal lines comprises a fourth connection section, a fifth connection section and a sixth connection section that are connected sequentially, the fourth connection section is electrically connected to the third section, the sixth connection section is electrically connected to the fourth section, the fifth connection section is connected between the fourth connection section and the sixth connection section, and both the fourth connection section and the sixth connection section extend in the first direction; and a plurality of second compensation signal lines located in the display area and extending in the first direction, wherein at least a portion of the plurality of second compensation signal lines is located on the extension of the second connection signal lines in the first direction. 13 . The array substrate according to claim 12 , wherein the second compensation signal line is electrically connected to

Assignees

Inventors

Classifications

  • H10D86/441Primary

    Interconnections, e.g. scanning lines · CPC title

  • organic, e.g. using organic light-emitting diodes [OLED] · CPC title

  • OLEDs integrated with inorganic light-sensitive elements, e.g. with inorganic solar cells or inorganic photodiodes · CPC title

  • H10D86/60Primary

    wherein the TFTs are in active matrices · CPC title

  • Interconnections, e.g. wiring lines or terminals · CPC title

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Frequently asked questions

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What does patent US12581740B2 cover?
An array substrate, a display panel and a display device. The array substrate includes: a hole area and a display area which is partially surrounding the hole area; a plurality of first signal lines located in the display area and including a plurality of first category signal lines and a plurality of second category signal lines; a plurality of first connection signal lines, each of which incl…
Who is the assignee on this patent?
Hefei Visionox Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10D86/441. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 17 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).