Device with dual isolation structure

Patent metadata

Field	Value
Publication number	US-12581701-B2
Application number	US-202117504051-A
Country	US
Kind code	B2
Filing date	Oct 18, 2021
Priority date	Oct 18, 2021
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to a semiconductor device with a dual isolation structure and methods of manufacture. The structure includes: a dual isolation structure including semiconductor material; and an active device region including a channel material and a gate metal material over the channel material. The channel material is between the dual isolation structure and the gate metal material includes a bottom surface not extending beyond a sidewall of the dual isolation structure.

First claim

What is claimed:

1 . A structure comprising:
a buffer layer above an underlying semiconductor material; a dual isolation structure comprising semiconductor material and located over the buffer layer, the dual isolation structure comprises non-vertical, angled outer sidewalls; and an active device region comprising a channel and a gate metal material over the channel material, the channel material being between and directly contacting inner sidewalls of the dual isolation structure and under the gate metal material and comprising a bottom surface over the buffer layer and not extending beyond the outer sidewalls of the dual isolation structure, and the gate metal material partially overlapping and directly contacting a top surface of the dual isolation structure; a two dimensional electron gas (2DEG) layer and a barrier layer, the 2DEG layer being in direct contact with both the barrier material and the channel material, both the 2DEG layer and the barrier material being between and in direct contact with the inner sidewalls of the dual isolation structure; an encapsulation layer extending over and in direct contact with a top surface of the buffer layer, the outer sidewalls and the top surface of the dual isolation structure, and further directly contacting a sidewall of the gate material adjacent to where the gate metal material partially overlaps the inner sidewalls of the dual isolation structure and directly contacts the top surface of the dual isolation structure, wherein the buffer layer is below and extends underneath and beyond outer edges of the outer sidewalls of the dual isolation structure and is directly contacting the underlying semiconductor material and the channel material.

2 . The structure of claim 1 , wherein the dual isolation structure comprises two isolation structures on a first set of opposing sides of the active device region.

3 . The structure of claim 2 , wherein the dual isolation structure comprises a same semiconductor material as the channel material and a barrier material on the channel material.

4 . The structure of claim 2 , wherein the dual isolation structure is absent on a second set of opposing sides of the active device region.

5 . The structure of claim 1 , wherein the doped semiconductor material comprises one of an inert gas species and a noble gas species.

6 . The structure of claim 1 , wherein the dual isolation structure comprises a surface coplanar with a barrier material over the channel material.

7 . The structure of claim 6 , wherein the non-vertical angled outer sidewalls of the dual isolation structure comprise an outer tapered, and the dual isolation structure further comprising an inner vertical sidewall, the channel material is between and in direct contact with the inner vertical sidewall, and the bottom surface of the gate metal material does not extend past the outer tapered sidewall.

8 . The structure of claim 7 , further comprising insulator material over the outer tapered sidewall of the dual isolation structure.

9 . The structure of claim 8 , further comprising an insulator liner directly contacting the outer tapered sidewall of the dual isolation structure and the underlying semiconductor material, and the insulator material being in direct contact with the insulator liner.

10 . The structure of claim 1 , wherein the channel material comprises GaN.

11 . A structure comprising:
a buffer layer above an underlying semiconductor material; an active device region comprising a channel material and a gate metal material, wherein a bottom surface of the channel material is over the buffer layer; a first isolation structure of doped semiconductor material on a first side of the channel material of the active device region and located over the buffer layer, the first isolation structure comprising an outer non-vertical, angled sidewall; a second isolation structure of the doped semiconductor material on a second, opposing side of the channel material of the active device region and located over the buffer layer, the second isolation structure comprising an outer non-vertical, angled sidewall; a two dimensional electron gas (2DEG) layer in direct contact with the channel material and a vertical inner sidewall of the first isolation structure and the second isolation structure; a barrier layer in direct contact with a top surface of the 2DEG layer, the vertical inner sidewalls of the first isolation structure and the second isolation structure, and an underside surface of the gate metal material; and an encapsulation layer extending over the first and second isolation structures, wherein the gate metal material partially overlaps a side edge of the first isolation structure and the second isolation structure and is completely over a top surface of the first isolation structure and the second isolation structure, the gate metal material being in direct contact with a top surface of the first and second isolation structures, wherein the encapsulation layer directly contacts the gate material adjacent to the gate metal material partially overlapping the side edge and directly contacts the outer non-vertical, angled sidewall of the first and second isolation structures, wherein the buffer layer is below and extends underneath and beyond outer edges of the dual isolation structure and is directly contacting the underlying semiconductor material and the channel material.

12 . The structure of claim 11 , wherein the active device region is devoid of isolation structures on a second set of opposing sidewalls.

13 . The structure of claim 11 , wherein the first isolation structure and the second isolation structure comprise a dual isolation structure composed of a same semiconductor material as the channel material of the active device region.

14 . The structure of claim 11 , wherein the dual isolation structure comprises a doped semiconductor material which has a damaged crystalline structure.

15 . The structure of claim 11 , wherein the first isolation structure and the second isolation structure each comprise an outer tapered sidewall comprising the non-vertical, angled sidewall, and a bottom surface of the gate metal material does not extend beyond the outer tapered sidewall of the first isolation structure and the second isolation structure.

16 . The structure of claim 11 , wherein the channel material comprises GaN.

17 . The structure of claim 11 , wherein a sidewall of the first isolation structure and a sidewall of the second isolation structure are lined with an insulator liner material.

18 . The structure of claim 17 , further comprising interlevel dielectric material in direct contact with the insulator liner material.

19 . A method comprising:
forming a buffer layer above an underlying semiconductor material; forming an active device region comprising a channel material and a gate metal material, wherein a bottom surface of the channel material is over the buffer layer; forming a first isolation structure of doped semiconductor material on a first side of the channel material of the active device region and located over the buffer layer, the first isolation structure comprising an outer non-vertical, angled sidewall; and forming a second isolation structure of the doped semiconductor material on a second, opposing side of the channel material of the active device region and located over the buffer layer, the second isolation structure comprising an outer non-vertical, angled sidewall, forming a two dimensional electron gas (2DEG) laye

Assignees

• Globalfoundries Us Inc

Inventors

• Rassel Richard J
• Kantarovsky Johnatan A
• He Zhong-Xiang
• Levy Mark D
• Abou-Khalil Michel J

Classifications

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D62/854

  further characterised by the dopants · CPC title

• H10D62/824

  comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions · CPC title

• H10D30/475 Primary

  having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title