Processor and operating method for a homogeneous dual computing system

Patent metadata

Field	Value
Publication number	US-12580764-B2
Application number	US-202318461780-A
Country	US
Kind code	B2
Filing date	Sep 6, 2023
Priority date	Nov 25, 2022
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A processor for building a homogeneous dual computing system is shown. The processor provides two homogeneous cores. One is used as a trusted core and the other is used as a master core. The trusted core has an access right to an isolated storage space of a system memory. The master core is a normal core that is prohibited from accessing the isolated storage space. The trusted core has a first cryptographic module. In response to a reset of the trusted core, the first cryptographic module operates for firmware verification. This is how the trusted core turns on the processor using trusted firmware.

First claim

What is claimed is:

1 . A processor for building a homogeneous dual computing system, comprising:
a trusted core, having an access right to an isolated storage space of a system memory; and a master core, which is homogeneous with the trusted core, and is one normal core prohibited from accessing the isolated storage space; wherein: the trusted core has a first cryptographic module; in response to a reset of the trusted core, the first cryptographic module operates for firmware verification and thereby the trusted core turns on the processor using trusted firmware; in response to resetting of all normal cores and the trusted core, the trusted core starts operations and all normal cores go to sleep; the trusted core operates the first cryptographic module to perform firmware signature verification to authenticate and run the trusted firmware, and further operates the first cryptographic module to perform basic input and output system verification to authenticate a trusted basic input and output system, and then wakes up the master core; and after being woken up, the master core runs the trusted basic input and output system.

2 . The processor as claimed in claim 1 , wherein:
after waking up the master core to run the trusted basic input and output system, the trusted core enters a sleep state; the trusted core in the sleep state is awakened by the master core after the master core running the trusted basic input and output system establishes a link between sockets or dies; and after being awakened by the master core, the trusted core runs the trusted firmware to operate the first cryptographic module to perform operating system verification on an operating system loaded on the trusted core, to authenticate and run a trusted operating system.

3 . The processor as claimed in claim 2 , wherein:
after being awakened by the master core to run the trusted firmware, the trusted core informs the master core that the trusted core has learned the link between sockets or dies and, in response to being acknowledged by the trusted core, the master core runs the trusted basic input and output system to operate a second cryptographic module in the master core to perform operating system verification on an operating system loaded onto the master core, to authenticate and run a host operating system.

4 . The processor as claimed in claim 3 , wherein:
the trusted core issues a secure inter-processor interrupt to safely wake up the master core to run the trusted basic input and output system; after running the trusted basic input and output system to establish the link between sockets or dies, the master core issues a secure inter-processor interrupt to safely wake up the trusted core to run the trusted firmware; and the trusted core issues a secure inter-processor interrupt to inform the master core that the trusted core has learned the link between sockets or dies.

5 . The processor as claimed in claim 4 , wherein:
the trusted core running the trusted operating system and the normal core running the host operating system communicate with each other by accessing a shared storage space of the system memory through secure inter-processor interrupts.

6 . The processor as claimed in claim 5 , further comprising:
an interrupt processing module, blocking or unblocking interrupts the normal cores issue to the trusted core according to interrupt types of the interrupts, wherein the interrupts unblocked by the interrupt processing module including point-to-point secure inter-processor interrupts, and multi-core synchronized external interrupts.

7 . The processor as claimed in claim 6 , wherein:
according to necessity, local internal interrupts of the trusted core are blocked by the interrupt processing module while other internal interrupts of the trusted core are allowed by the interrupt processing module.

8 . The processor as claimed in claim 7 , further comprising:
a model-specific register, which is programmed when the processor starts up, to make sure that one bit of the model-specific register corresponds to one interrupt type to indicate whether to block or unblock interrupts of the corresponding interrupt type.

9 . The processor as claimed in claim 5 , which is a single-die processor, wherein the master core and the trusted core are provided on the same die.

10 . The processor as claimed in claim 1 , which is a multi-die processor further comprising:
a first die, temporarily planned to provide the trusted core and the master core, so that on the first die, the master core runs the trusted basic input and output system for link establishment; dies other than the first die, temporarily planned to provide an on-die trusted core and an on-die master core on each die; each on-die trusted core performs firmware verification and runs verified firmware to perform basic input and output system verification, and each on-die master core runs a verified basic input and output system for link establishment; and after being linked together, all dies are unified to provide a system trusted core and a system master core, wherein a trusted operating system is loaded onto the system trusted core and run by the system trusted core, and a host operating system is loaded onto the system master core and run by the system master core.

11 . A method for operating a homogeneous dual computing system, comprising:
planning a processor with multiple cores to provide a trusted core that has an access right to an isolated storage space of a system memory, and a master core which is homogeneous with the trusted core and is a normal core prohibited from accessing the isolated storage space; and in response to a reset of the trusted core, a first cryptographic module of the trusted core is operated to perform firmware verification and thereby the trusted core turns on the processor using trusted firmware; wherein:
in response to a reset of all normal cores and the trusted core, the trusted core starts operations and all normal cores go to sleep;
the trusted core operates the first cryptographic module to perform firmware signature verification to authenticate and run the trusted firmware, and further operates the first cryptographic module to perform basic input and output system verification to authenticate a trusted basic input and output system, and then wakes up the master core; and
after being woken up, the master core runs the trusted basic input and output system.

12 . The method as claimed in claim 11 , wherein:
after waking up the master core to run the trusted basic input and output system, the trusted core enters a sleep state; the trusted core in the sleep state is awakened by the master core after the master core running the trusted basic input and output system establishes a link between sockets or dies; and after being awakened by the master core, the trusted core runs the trusted firmware to operate the first cryptographic module to perform operating system verification on an operating system loaded on the trusted core, to authenticate and run a trusted operating system.

13 . The method as claimed in claim 12 , wherein:
after being awakened by the master core to run the trusted firmware, the trusted core informs the master core that the trusted core has learned the link between sockets or dies and, in response to being acknowledged by the trusted core, the master core runs the trusted basic input and output system to operate a second cryptographic module in the master core to perform operating system verification on an operating system loaded onto the master core, to authenticate and run a host operating system.

Assignees

• Shanghai Zhaoxin Semiconductor Co Ltd

Inventors

• Huang Zhenhua
• Guan Yingbing
• Li Yanting
• Xue Gangru
• Li Mingxiu

Classifications

• H04L9/3234

  involving additional secure or trusted devices, e.g. TPM, smartcard, USB or software token (network architectures or network communication protocols for supporting authentication of entities using an additional device in a packet data network H04L63/0853) · CPC title

• H04L9/32 Primary

  including means for verifying the identity or authority of a user of the system {or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials} · CPC title