Differential successive approximation register analog-to-digital converter with dynamic input common-mode voltage control and associated method

Patent metadata

Field	Value
Publication number	US-12580583-B2
Application number	US-202418673343-A
Country	US
Kind code	B2
Filing date	May 24, 2024
Priority date	May 24, 2024
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A differential successive approximation register (SAR) analog-to-digital converter (ADC) includes a comparator circuit, a sampling circuit, a first capacitive digital-to-analog converter (DAC), a second capacitive DAC, a SAR logic circuit, and a common-mode voltage control circuit. The sampling circuit samples a differential voltage input to generate and output a differential comparator input to the comparator circuit during a sample phase of the differential SAR ADC. The first and second capacitive DACs are coupled to a non-inverting input terminal and an inverting input terminal of the comparator circuit, respectively. The SAR logic circuit controls the first and second capacitive DACs during a SAR phase of the differential SAR ADC. The common-mode voltage control circuit dynamically adjusts an input common-mode voltage of the comparator circuit, wherein the input common-mode voltage of the comparator circuit has different voltage levels during the sample phase and the SAR phase.

First claim

What is claimed is:

1 . A differential successive approximation register (SAR) analog-to-digital converter (ADC), comprising:
a comparator circuit, having a non-inverting input terminal and an inverting input terminal; a sampling circuit, arranged to sample a differential voltage input to generate and output a differential comparator input to the comparator circuit during a sample phase of the differential SAR ADC; a first capacitive digital-to-analog converter (DAC), coupled to the non-inverting input terminal of the comparator circuit; a second capacitive DAC, coupled to the inverting input terminal of the comparator circuit; a SAR logic circuit, arranged to control the first capacitive DAC and the second capacitive DAC during a SAR phase of the differential SAR ADC; and a common-mode voltage control circuit, arranged to dynamically adjust an input common-mode voltage of the comparator circuit, wherein the input common-mode voltage of the comparator circuit has a first voltage level during the sample phase and a second voltage level during the SAR phase, and the second voltage level is different from the first voltage level.

2 . The differential SAR ADC of claim 1 , wherein the second voltage level is lower than the first voltage level.

3 . The differential SAR ADC of claim 1 , wherein the second voltage level is higher than the first voltage level.

4 . The differential SAR ADC of claim 1 , wherein the common-mode voltage control circuit comprises:
a first common-mode capacitor, having a first plate and a second plate, wherein the first plate of the first common-mode capacitor is coupled to the non-inverting input terminal of the comparator circuit; a second common-mode capacitor, having a first plate and a second plate, wherein the first plate of the second common-mode capacitor is coupled to the inverting input terminal of the comparator circuit; a first switch circuit, arranged to couple the second plate of the first common-mode capacitor to a first reference voltage during the sample phase, and couple the second plate of the first common-mode capacitor to a second reference voltage during the SAR phase, wherein the second reference voltage is different from the first reference voltage; a second switch circuit, arranged to couple the second plate of the second common-mode capacitor to the first reference voltage during the sample phase, and couple the second plate of the second common-mode capacitor to the second reference voltage during the SAR phase; and a common-mode capacitor control logic circuit, arranged to control configurations of the first switch circuit and the second switch circuit during the sample phase and the SAR phase.

5 . The differential SAR ADC of claim 4 , wherein the first reference voltage is higher than the second reference voltage.

6 . The differential SAR ADC of claim 4 , wherein the first reference voltage is lower than the second reference voltage.

7 . The differential SAR ADC of claim 1 , wherein the differential SAR ADC is a top-plate sampling differential SAR ADC.

8 . A differential successive approximation register (SAR) analog-to-digital conversion method, comprising:
during a sample phase of a differential SAR analog-to-digital conversion operation,
sampling a differential voltage input to generate and output a differential comparator input to a comparator circuit, wherein the comparator circuit has a non-inverting input terminal and an inverting input terminal; and
setting an input common-mode voltage of the comparator circuit by a first voltage level; and
during a SAR phase of the differential SAR analog-to-digital conversion operation,
controlling a first capacitive digital-to-analog converter (DAC) that is coupled to the non-inverting input terminal of the comparator circuit and a second capacitive DAC that is coupled to the inverting input terminal of the comparator circuit; and
adjusting the input common-mode voltage of the comparator circuit to have a second voltage level, wherein the second voltage level is different from the first voltage level.

9 . The differential SAR analog-to-digital conversion method of claim 8 , wherein the second voltage level is lower than the first voltage level.

10 . The differential SAR analog-to-digital conversion method of claim 8 , wherein the second voltage level is higher than the first voltage level.

11 . The differential SAR analog-to-digital conversion method of claim 8 , wherein a first plate of a first common-mode capacitor is coupled to the non-inverting input terminal of the comparator circuit, and a first plate of a second common-mode capacitor is coupled to the inverting input terminal of the comparator circuit; setting the input common-mode voltage of the comparator circuit by the first voltage level comprises:
coupling a second plate of the first common-mode capacitor to a first reference voltage; and coupling a second plate of the first common-mode capacitor to the first reference voltage;
adjusting the input common-mode voltage of the comparator circuit to have the second voltage level comprises:
coupling the second plate of the first common-mode capacitor to a second reference voltage, wherein the second reference voltage is different from the first reference voltage; and
coupling the second plate of the first common-mode capacitor to the second reference voltage.

12 . The differential SAR analog-to-digital conversion method of claim 11 , wherein the first reference voltage is higher than the second reference voltage.

13 . The differential SAR analog-to-digital conversion method of claim 11 , wherein the first reference voltage is lower than the second reference voltage.

14 . The differential SAR analog-to-digital conversion method of claim 8 , wherein the differential SAR analog-to-digital conversion method employs a top-plate sampling technique.

Assignees

• Airoha Tech Corp

Inventors

• Shen Wei-Chen
• Kang Tzung-Hung

Classifications

• H03M1/468 Primary

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M3/04 Primary

  Differential modulation with several bits {, e.g. differential pulse code modulation [DPCM] (H03M3/30 takes precedence)} · CPC title