Scaling-friendly, analog correlators using charge-based margin propagation

Patent metadata

Field	Value
Publication number	US-12580577-B2
Application number	US-202318485939-A
Country	US
Kind code	B2
Filing date	Oct 12, 2023
Priority date	Oct 12, 2022
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A non-multiply-accumulate (non-MAC) charge-based analog correlator system including a sampler circuit block, an operand generation circuit block, and a margin propagation (MP) correlation computation circuit block is disclosed. The sampler circuit block is configured to sample a plurality of input analog signals. The operand generation circuit block is configured to generate operands based on the sampled plurality of input analog signals, and the margin propagation (MP) correlation computation circuit block is configured to generate correlated output signals based on the operands and using calculations in a charge domain.

First claim

What is claimed is:

1 . A non-multiply-accumulate (non-MAC) charge-based analog correlator system comprising:
a sampler circuit block configured to sample a plurality of input analog signals; an operand generation circuit block configured to generate operands based on the sampled plurality of input analog signals; and a margin propagation (MP) correlation computation circuit block for the non-multiply-accumulate (non-MAC) charge-based analog correlator system, wherein the MP correlation computation circuit block is configured to: generate correlated output signals based on the operands and using calculations in a charge domain; and implement a rectifying-linear-unit (ReLU)-based MP function.

2 . The non-MAC charge-based analog correlator system of claim 1 , wherein the operand generation circuit block comprises a plurality of stacked capacitors configured to generate the operands.

3 . The non-MAC charge-based analog correlator system of claim 1 , wherein the operand generation circuit block is configured to generate quadrant operands, and the MP correlation computation circuit block is configured to generate the correlated output signals based on the quadrant operands.

4 . The non-MAC charge-based analog correlator system of claim 1 , wherein the sampler circuit block is further configured to generate analog delay in the sampled plurality of input analog signals.

5 . The non-MAC charge-based analog correlator system of claim 4 , wherein the sampler circuit block comprises cascaded delay elements configured to generate the analog delay.

6 . The non-MAC charge-based analog correlator system of claim 4 , wherein the sampler circuit block is configured to generate the analog delay based on tree distribution.

7 . The non-MAC charge-based analog correlator system of claim 1 , wherein the sampler circuit block comprises a 2-layer circuit configured to process a phase of the input analog signals.

8 . The non-MAC charge-based analog correlator system of claim 1 , wherein the margin propagation (MP) correlation computation circuit block includes a signal path and a charge transfer path.

9 . The non-MAC charge-based analog correlator system of claim 8 , wherein the signal path is separate from the charge transfer path.

10 . The non-MAC charge-based analog correlator system of claim 1 , wherein the input analog signals correspond with radar signals, code division communication signals, or spectrum sensing signals.

11 . The non-MAC charge-based analog correlator system of claim 1 , wherein the non-MAC charge-based analog correlator system is an integrated circuit (IC) implemented in a complementary metal oxide semiconductor (CMOS).

12 . A method, comprising:
generating a non-multiply-accumulate (non-MAC) charge-based analog correlator system comprising a sampler circuit block, an operand generation circuit block, and a margin propagation (MP) correlation computation circuit block; configuring the sampler circuit block to sample a plurality of input analog signals; configuring the operand generation circuit block to generate operands based on the sampled plurality of input analog signals; and configuring the MP correlation computation circuit block to: generate correlated output signals based on the operands and using calculations in a charge domain; and implement a rectifying-linear-unit (ReLU)-based MP function.

13 . The method of claim 12 , further comprising configuring the sampler circuit block to include a 2-layer circuit for processing each phase of an input analog signal of the input analog signals.

14 . The method of claim 12 , further comprising configuring a clock signal generator to generate a clock signal as a multi-phase non-overlapping clock signal.

15 . The method of claim 12 , further comprising configuring the operand generation circuit block to include a plurality of stacked capacitors.

16 . The method of claim 12 , further comprising:
configuring the MP correlation computation circuit block to include a signal path and a charge transfer path; and configuring the MP correlation computation circuit block to correlate an input analog signal of the input analog signals, and wherein the signal path is separate from the charge transfer path.

17 . The method of claim 12 , further comprising implementing the non-MAC charge-based analog correlator system as an integrated circuit (IC) using a complementary metal oxide semiconductor (CMOS).

18 . The method of claim 12 , further comprising configuring the sampler circuit block to generate analog delay in the sampled plurality of input analog signals.

19 . The method of claim 18 , wherein the sampler circuit block comprises cascaded delay elements configured to generate the analog delay.

Assignees

• Washington University St Louis
• Univ Oregon State

Inventors

• Nagulu Aravind
• Chakrabartty Shantanu
• Natarajan Arun

Classifications

• G01S13/284

  using coded pulses · CPC title

• G01S7/32

  Shaping echo pulse signals; Deriving non-pulse signals from echo pulse signals · CPC title

• G01S7/2806

  Employing storage or delay devices which preserve the pulse form of the echo signal, e.g. for comparing and combining echoes received during different periods · CPC title

• G01S7/03

  Details of HF subsystems specially adapted therefor, e.g. common to transmitter and receiver · CPC title

• H03M1/124 Primary

  Sampling or signal conditioning arrangements specially adapted for A/D converters · CPC title