Voltage converter with regulated switching frequency and minimum on time override

Patent metadata

Field	Value
Publication number	US-12580469-B2
Application number	US-202418591723-A
Country	US
Kind code	B2
Filing date	Feb 29, 2024
Priority date	Mar 3, 2023
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

Systems and methods for a voltage converter are described. A controller can include determining a pulse width modulation (PWM) on time duration being used for operating a voltage regulator. The controller can determine a switching frequency being used for operating the voltage regulator. The controller can determine whether the PWM on time duration is greater than or less than an on time reference. The controller can, in response to determining that the PWM on time duration is less than the on time reference, increase a voltage window for a PWM signal being used to operate the voltage regulator. The controller can, in response to determining that the PWM on time duration is greater than the on time reference, perform a frequency locked loop (FLL) to regulate the switching frequency.

First claim

What is claimed is:

1 . A method of operating a voltage regulator, the method comprising:
determining a pulse width modulation (PWM) on time duration being used for operating the voltage regulator; determining a switching frequency being used for operating the voltage regulator; determining whether the PWM on time duration is greater than or less than an on time reference; in response to determining that the PWM on time duration is less than the on time reference, increasing a voltage window for a PWM signal being used to operate the voltage regulator; and
in response to determining that the PWM on time duration is greater than the on time reference, performing a frequency locked loop (FLL) to regulate the switching frequency.

2 . The method of claim 1 , wherein performing the FLL comprises:
determining whether the switching frequency is greater than or less than a first reference switching frequency; in response to determining that the switching frequency is less than the first reference switching frequency, decreasing the voltage window; in response to determining that the switching frequency is greater than the first reference switching frequency, determining whether the switching frequency is greater than or less than a second reference switching frequency, wherein the second reference switching frequency is greater than the first reference switching frequency; and in response to determining that the switching frequency is greater than the second reference switching frequency, increasing the voltage window.

3 . The method of claim 1 , further comprising:
determining that a new PWM cycle has occurred; determining the PWM on time duration comprises determining a PWM on time of a PWM signal in a completed PWM cycle previous to the new PWM cycle; and determining the switching frequency comprises determining a switching frequency of the PWM signal in the completed PWM cycle previous to the new PWM cycle.

4 . The method of claim 2 , wherein determining the switching frequency comprises:
determining a PWM off time duration being used for operating the voltage regulator; summing the PWM on time and the PWM off time to determine a cycle time; and determining a reciprocal of the cycle time to determine the switching frequency.

5 . The method of claim 1 , wherein the on time reference is a first on time reference, and performing the FLL comprises:
in response to determining that the PWM on time duration is greater than the first on time reference, determining whether the switching frequency is greater than or less than a first reference switching frequency; in response to determining that the switching frequency is less than the first reference switching frequency, determining whether the PWM on time duration is greater than or less than a second on time reference, wherein the second on time reference is greater than the first on time reference; in response to determining that the PWM on time duration is greater than the second on time reference, decreasing the voltage window; in response to determining that the switching frequency is greater than the first reference switching frequency, determining whether the switching frequency is greater than or less than a second reference switching frequency; and in response to determining that the switching frequency is greater than the second reference switching frequency, increasing the voltage window.

6 . The method of claim 1 , wherein:
increasing the voltage window for the PWM signal decreases the switching frequency; and decreasing the voltage window for the PWM signal increases the switching frequency.

7 . The method of claim 1 , wherein the voltage regulator is a hysteretic current mode buck regulator.

8 . A semiconductor device comprising:
a controller configured to:
determine a pulse width modulation (PWM) on time duration being used for operating a voltage regulator;
determine a switching frequency being used for operating the voltage regulator;
determine whether the PWM on time duration is greater than or less than an on time reference;
in response to the determination that the PWM on time duration is less than the on time reference, increase a voltage window for a PWM signal being used to operate the voltage regulator; and
in response to the determination that the PWM on time duration is greater than the on time reference, perform a frequency locked loop (FLL) to regulate the switching frequency.

9 . The semiconductor device of claim 8 , wherein the controller is further configured to:
determine whether the switching frequency is greater than or less than a first reference switching frequency; in response to the determination that the switching frequency is less than the first reference switching frequency, decrease the voltage window; in response to the determination that the switching frequency is greater than the first reference switching frequency, determine whether the switching frequency is greater than or less than a second reference switching frequency, wherein the second reference switching frequency is greater than the first reference switching frequency; and in response to the determination that the switching frequency is greater than the second reference switching frequency, increase the voltage window.

10 . The semiconductor device of claim 8 , wherein the controller is further configured to:
determine that a new PWM cycle has occurred; determine the PWM on time duration by a determination of a PWM on time of a PWM signal in a completed PWM cycle previous to the new PWM cycle; and determine the switching frequency by a determination of a switching frequency of the PWM signal in the completed PWM cycle previous to the new PWM cycle.

11 . The semiconductor device of claim 8 , wherein the controller is configured to:
determine a PWM off time duration being used for operating the voltage regulator; sum the PWM on time and the PWM off time to determine a cycle time; and determine a reciprocal of the cycle time to determine the switching frequency.

12 . The semiconductor device of claim 8 , wherein the on time reference is a first on time reference, and the controller is further configured to:
in response to determination that the PWM on time duration is greater than the first on time reference, determine whether the switching frequency is greater than or less than a first reference switching frequency; in response to determination that the switching frequency is less than the first reference switching frequency, determine whether the PWM on time duration is greater than or less than a second on time reference, wherein the second on time reference is greater than the first on time reference; in response to determination that the PWM on time duration is greater than the second on time reference, decrease the voltage window; in response to determination that the switching frequency is greater than the first reference switching frequency, determine whether the switching frequency is greater than or less than a second reference switching frequency; and in response to determination that the switching frequency is greater than the second reference switching frequency, increase the voltage window.

13 . The semiconductor device of claim 8 , wherein:
an increase of the voltage window for the PWM signal decreases the switching frequency; and a decrease of the voltage window for the PWM signal increases the switching frequency.

14 . The semiconductor device of claim 8 , wherein a power stage, a driver circuit and the controller are parts of a hysteretic current mode buck regulator.

Assignees

• Renesas Electronics America Inc

Inventors

• Houston Michael Jason
• Schroeder Warren Richard

Classifications

• H02M3/157

  with digital control · CPC title

• H02M1/088

  for the simultaneous control of series or parallel connected semiconductor devices · CPC title

• H02M3/155

  using semiconductor devices only · CPC title

• H02M1/08

  Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters · CPC title

• H02M1/0012

  Control circuits using digital or numerical techniques (in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873) · CPC title