Additional silicide layer on top of staircase for 3D NAND WL contact connection

Patent metadata

Field	Value
Publication number	US-12580018-B2
Application number	US-202117549685-A
Country	US
Kind code	B2
Filing date	Dec 13, 2021
Priority date	Oct 28, 2021
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

An embodiment of an apparatus may include a substrate, a memory array of vertical 3D NAND strings formed in the substrate, a staircase region formed in the substrate, a polysilicon wordline extended horizontally into the staircase region, a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline, and a punch stop layer disposed between the wordline contact and the polysilicon wordline. Other embodiments are disclosed and claimed.

First claim

What is claimed is:

1 . An apparatus, comprising:
a substrate formed from alternating layers of polysilicon and an insulator material; a memory array of vertical 3D NAND strings formed in the substrate; a staircase region formed in the substrate, the staircase region further including respective pockets formed in respective insulator material layers between respective polysilicon layers; a polysilicon wordline extended horizontally into the staircase region; a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline; a silicide layer disposed on the substrate to cover the polysilicon wordline that extends into the staircase region and to partially fill the respective pockets; and a punch stop material disposed between the wordline contact and the polysilicon wordline.

2 . The apparatus of claim 1 , wherein the punch stop material comprises silicide.

3 . The apparatus of claim 2 , wherein the silicide layer comprises tungsten silicide.

4 . The apparatus of claim 1 , wherein the insulator material comprises an oxide.

5 . The apparatus of claim 1 , the respective pockets further comprising:
a first pocket formed in the insulator material between two corresponding polysilicon layers adjacent to the punch stop material.

6 . The apparatus of claim 1 , wherein the punch stop material at least partially wraps around an end edge of the polysilicon wordline in the staircase region.

7 . A method, comprising:
forming a substrate from alternating layers of polysilicon and an insulator material; forming a memory array of vertical 3D NAND strings in the substrate; forming a staircase region in the substrate; forming respective pockets in the staircase region in the substrate in respective insulator material layers between respective polysilicon layers; forming a polysilicon wordline extended horizontally into the staircase region; forming a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline; depositing a silicide layer on the substrate to cover the polysilicon wordline that extends into the staircase region and to partially fill the respective pockets; and disposing punch stop material between the wordline contact and the polysilicon wordline.

8 . The method of claim 7 , wherein the punch stop material comprises silicide.

9 . The method of claim 8 , wherein the silicide layer comprises tungsten silicide.

10 . The method of claim 7 , wherein the insulator material comprises an oxide.

11 . The method of claim 7 , further comprising:
wet etching the silicide layer to remove silicide material from respective sidewalls of the pockets while leaving silicide material on the polysilicon wordline that extends into the staircase region.

12 . The method of claim 7 , wherein the punch stop material at least partially wraps around an end edge of the polysilicon wordline in the staircase region.

13 . A system, comprising:
a processor and a three-dimensional (3D) memory device coupled to the processor, wherein the 3D memory device includes: a substrate formed from alternating layers of polysilicon and an insulator material; a memory array of vertical 3D NAND strings formed in the substrate; a staircase region formed in the substrate, the staircase region further including respective pockets formed in respective insulator material layers between respective polysilicon layers; a polysilicon wordline extended horizontally into the staircase region; a wordline contact extended vertically through the staircase region to make electrical contact with the polysilicon wordline; a silicide layer deposited on the substrate to cover the polysilicon wordline that extends into the staircase region and to partially fill the respective pockets; and a punch stop material disposed between the wordline contact and the polysilicon wordline.

14 . The system of claim 13 , wherein the punch stop material comprises silicide.

15 . The system of claim 14 , wherein the silicide layer comprises tungsten silicide.

16 . The system of claim 13 , wherein the insulator material comprises an oxide.

17 . The system of claim 13 , wherein the respective pockets of the 3D memory device further include:
a first pocket formed in the insulator material between two corresponding polysilicon layers adjacent to the punch stop material.

18 . The system of claim 13 , wherein the punch stop material at least partially wraps around an end edge of the polysilicon wordline in the staircase region.

Assignees

• Intel NDTM US LLC

Inventors

• Liu Liu
• Ding Junchao
• Liu Yingming
• Sel Jong Sun
• Ma Yixin
• Lee Jinwoo
• Lin Xi

Classifications

• H10B43/35

  with cell select transistors, e.g. NAND · CPC title

• H10B43/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• H10B41/35

  with a cell select transistor, e.g. NAND · CPC title

• H10B41/27

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title

• G11C8/14

  Word line organisation; Word line lay-out · CPC title