Pixel driving circuit and display panel

Patent metadata

Field	Value
Publication number	US-12579941-B2
Application number	US-202519089049-A
Country	US
Kind code	B2
Filing date	Mar 25, 2025
Priority date	Sep 29, 2021
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A pixel driving circuit and a display panel are provided, the circuit includes a driving transistor connected to a first and third nodes; a first transistor connected to a second node to output a data voltage to the second node in response to a first scan signal; a second transistor connected to the first and third nodes; a fifth transistor connected to the second node to output a reference voltage to the second node in response to a first reset signal; a seventh transistor connected to the third and fourth nodes to electrically communicate the third node with the fourth node in response to a light emitting control signal; and a storage capacitor, connected to the first and second nodes to store the data voltage and a threshold voltage of the driving transistor.

First claim

What is claimed is:

1 . A pixel driving circuit, comprising:
a driving transistor, connected to a first node and a third node; a first transistor, connected to a second node, configured to output a data voltage to the second node in response to a first scan signal; a second transistor, connected to the first node and the third node; a fifth transistor, connected to the second node, configured to output a reference voltage to the second node in response to a first reset signal; a seventh transistor, connected to the third node and a fourth node, configured to electrically communicate the third node with the fourth node in response to a light emitting control signal; and a storage capacitor, connected to the first node and the second node, wherein the storage capacitor is configured to store the data voltage and a threshold voltage of the driving transistor.

2 . The pixel driving circuit according to claim 1 , further comprising a fourth transistor, wherein a first electrode of the fourth transistor is configured to load an initialization voltage, and a second electrode of the fourth transistor is connected to the first node.

3 . The pixel driving circuit according to claim 1 , wherein a channel region of the fifth transistor comprises a first sub-channel region and a second sub-channel region, and a conductive second conductive lead connecting the first sub-channel region and the second sub-channel region in series; the first sub-channel region and the second sub-channel region are arranged in a row direction.

4 . The pixel driving circuit according to claim 1 , further comprising an eighth transistor, wherein a first electrode of the eighth transistor is configured to load an initialization voltage, and a second electrode of the eighth transistor is connected to the fourth node.

5 . The pixel driving circuit according to claim 4 , wherein a display panel is provided with a first reset lead;
wherein the first reset lead overlaps with a channel region of the eighth transistor, such that an overlapping part is reused as a gate of the eighth transistor.

6 . The pixel driving circuit according to claim 4 , wherein materials of active layers of the first transistor, the driving transistor, the fifth transistor, the seventh transistor, and the eighth transistor are all polysilicon semiconductor materials.

7 . The pixel driving circuit according to claim 1 , wherein the storage capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate is located in a first gate layer of a display panel, and the second electrode plate is located in a second gate layer of the display panel;
wherein the second electrode plates adjacently arranged along a row direction are independently provided.

8 . The pixel driving circuit according to claim 7 , wherein the display panel is provided with a second gate layer, the second gate layer is provided with a power distribution lead extending along the row direction, and the power distribution lead is electrically connected to at least one first power supply voltage lead of the display panel.

9 . The pixel driving circuit according to claim 1 , wherein the display panel is provided with a second metal wiring layer, the second metal wiring layer is provided with a first power supply voltage lead, a data lead, and a transfer metal structure, and a pixel electrode of a light-emitting element is connected to the transfer metal structure through a via hole.

10 . The pixel driving circuit according to claim 1 , wherein the display panel comprises a base substrate, a driving circuit layer, and a pixel layer sequentially stacked;
wherein the pixel driving circuit is provided in the driving circuit layer; the pixel layer comprises a red light emitting element, a green light emitting element, and a blue light emitting element; and a pixel electrode of a light-emitting element is electrically connected to the pixel driving circuit.

11 . The pixel driving circuit according to claim 1 , wherein during a threshold voltage compensation phase, the first node is charged to VDD+Vth; wherein the VDD is a first power supply voltage, and the Vth is the threshold voltage of the driving transistor.

12 . The pixel driving circuit according to claim 7 , wherein the pixel driving circuit is applied to a display panel, and the display panel comprises a base substrate;
wherein the storage capacitor further comprises a third electrode plate and a fourth electrode plate, and the first electrode plate, the second electrode plate, the third electrode plate and the fourth electrode plate are sequentially stacked on a side of the base substrate; the display panel further comprises a first passivation layer and a first planarization layer sequentially stacked on a side of the third electrode plate away from the base substrate, and the fourth electrode plate is arranged on a side of the first planarization layer away from the base substrate; the first planarization layer comprises at least a first portion and a second portion, and the first portion of the first planarization layer is sandwiched between the third electrode plate and the fourth electrode plate; the second portion of the first planarization layer does not overlap with the third electrode plate and the fourth electrode plate; and a thickness of the first portion is less than a thickness of the second portion.

13 . The pixel driving circuit according to claim 12 , wherein the thickness of the first portion of the first planarization layer is 0 to expose the first passivation layer.

14 . The pixel driving circuit according to claim 12 , wherein the first planarization layer comprises a third portion sandwiched between the first portion and the second portion, an inner edge of the third portion is located within an overlapping region of the third electrode plate and the fourth electrode plate, and an outer edge of the third portion does not overlap with any one of the third electrode plate and the fourth electrode plate.

15 . The pixel driving circuit according to claim 3 , wherein the pixel driving circuit is applied to a display panel, and a display panel is provided with a first reset lead;
wherein the first reset lead overlaps with a channel region of the fifth transistor, such that an overlapping part is reused as a gate of the fifth transistor.

16 . The pixel driving circuit according to claim 15 , wherein orthographic projections of the first sub-channel region and the second sub-channel region on a base substrate of the display panel are located within an orthographic projection of the first reset lead on the base substrate.

17 . The pixel driving circuit according to claim 7 , wherein the first electrode plate covers a channel region of the driving transistor to be reused as a gate of the driving transistor.

18 . The pixel driving circuit according to claim 12 , wherein the first electrode plate is provided with a thirteenth bottom via hole region, and the thirteenth bottom via hole region is electrically connected to the third electrode plate through a via hole.

19 . The pixel driving circuit according to claim 1 , wherein the pixel driving circuit is applied to a display panel, and the display panel comprises a first gate layer;
a gate of the second transistor comprises a first gate located at the first gate layer, the first gate layer is provided with a second scan lead configured to load a second scan signal, and the second scan lead is electrically connected to the first gate of the second transis

Assignees

• Boe Technology Group Co Ltd

Inventors

• Wang Li
• Feng Yu
• Zhang Hao

Classifications

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title