Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12579940-B2
Application number	US-202519011035-A
Country	US
Kind code	B2
Filing date	Jan 6, 2025
Priority date	Jan 10, 2022
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A display substrate includes: a base substrate and a plurality of sub-pixels arranged on the base substrate, the sub-pixel include a sub-pixel driving circuit, the sub-pixel driving circuit includes: a first transistor, a driving transistor, and a first conductive connection portion; a first electrode of the first transistor is coupled to a second electrode of the driving transistor, a second electrode of the first transistor and a first end portion of the first conductive connection portion are arranged at different layers, the second electrode of the first transistor and the first end portion of the first conductive connection portion are coupled through a via hole; a second end portion of the first conductive connection portion is coupled to a gate electrode of the driving transistor.

First claim

What is claimed is:

1 . A display substrate, comprising: a base substrate and a plurality of sub-pixels arranged on the base substrate, wherein the display substrate further includes a data line; the sub-pixel include a sub-pixel driving circuit, the sub-pixel driving circuit includes: a first transistor, a fourth transistor, a driving transistor, and a first conductive connection portion;
a first electrode of the first transistor is coupled to a second electrode of the driving transistor, a second electrode of the first transistor and a first end portion of the first conductive connection portion are arranged at different layers, the second electrode of the first transistor and the first end portion of the first conductive connection portion are coupled through a via hole; a second end portion of the first conductive connection portion is coupled to a gate electrode of the driving transistor; a first electrode of the fourth transistor is coupled to a corresponding data line, a second electrode of the fourth transistor is coupled to a first electrode of the driving transistor; at least part of an orthographic projection of the gate electrode of the first transistor on the base substrate is located between an orthographic projection of the first end portion on the base substrate and an orthographic projection of the gate electrode of the driving transistor on the base substrate; wherein the first conductive connection portion includes at least a part extending along a first direction; the second electrode of the first transistor includes a first portion, a second portion and a third portion coupled sequentially, each of the first portion and the third portion includes at least a part extending along a second direction, the second portion includes at least a part extending along the first direction, the first direction intersects the second direction; the third portion is coupled to the first end portion; wherein the display substrate further includes an initialization signal line; the sub-pixel driving circuit further includes a second transistor, and the first electrode of the second transistor is coupled to the initialization signal line, and the second electrode of the second transistor is coupled to the first end portion; an orthographic projection of the first end portion on the base substrate is located between an orthographic projection of the first electrode of the second transistor on the base substrate and the orthographic projection of the gate electrode of the first transistor on the base substrate; wherein the sub-pixel driving circuit further includes a second conductive connection portion; the first electrode of the second transistor is coupled to the initialization signal line through the second conductive connection portion; the second transistor includes a second active layer, the second active layer includes a second channel portion, an orthographic projection of the second channel portion on the base substrate at least partially overlaps an orthographic projection of the second conductive connection portion on the base substrate.

2 . The display substrate according to claim 1 , wherein the first transistor includes a first active layer, and the first active layer includes a first channel portion, the orthographic projection of the first conductive connection portion on the base substrate overlaps the orthographic projection of the first channel portion on the base substrate.

3 . The display substrate according to claim 1 , wherein the second electrode of the second transistor includes a fourth portion extending along the first direction; the fourth portion and the second portion are at least partially staggered along the second direction.

4 . The display substrate according to claim 1 , wherein the sub-pixel further includes:
a shielding pattern, wherein an orthographic projection of the shielding pattern on the base substrate at least partially overlaps an orthographic projection of the second electrode of the first transistor on the base substrate, and also at least partially overlaps an orthographic projection of the second electrode of the second transistor on the base substrate.

5 . The display substrate according to the claim 4 , wherein the orthographic projection of the shielding pattern on the base substrate covers an orthographic projection of the second portion on the base substrate; the orthographic projection of the shielding pattern on the base substrate at least partially overlaps an orthographic projection of the first portion on the base substrate, and at least partially overlaps an orthographic projection of the third portion on the base substrate.

6 . The display substrate according to claim 4 , wherein the display substrate further includes a power line; an orthographic projection of the power line on the base substrate at least partially overlaps the orthographic projection of the second electrode of the first transistor on the base substrate; the orthographic projection of the power line on the base substrate at least partially overlaps the orthographic projection of the second electrode of the second transistor on the base substrate.

7 . The display substrate according to the claim 6 , wherein, there is a first overlapping area between the orthographic projection of the shielding pattern on the base substrate and the orthographic projection of the power line on the base substrate, the shielding pattern is coupled to the power line through a first via hole in the first overlapping area;
an orthographic projection of the first via hole on the base substrate is located between orthographic projections of gate electrode of first transistors in adjacent sub-pixel driving circuits along the second direction on the base substrate.

8 . The display substrate according to claim 4 , wherein, the first transistor includes a first active layer, and the first active layer includes two first channel portions, and a conductor portion coupled to the two first channel portions respectively;
the orthographic projection of the shielding pattern on the base substrate at least partially overlaps an orthographic projection of a conductor portion in an adjacent sub-pixel driving circuit on the base substrate.

9 . The display substrate according to the claim 8 , wherein the shielding pattern includes a first shielding portion and a second shielding portion, and the first shielding portion includes at least part extending along the first direction, the second shielding portion includes at least part extending along the second direction;
an orthographic projection of the first shielding portion on the base substrate at least partially overlaps the orthographic projection of the second electrode of the first transistor on the base substrate, and also at least partially overlaps the orthographic projection of the second electrode of the second transistor on the base substrate; an orthographic projection of the second shielding portion on the base substrate at least partially overlaps the orthographic projections of the conductor portion in the adjacent sub-pixel driving circuit on the base substrate.

10 . The display substrate according to the claim 9 , wherein, at least part of the orthographic projection of the first shielding portion on the base substrate is located between the orthographic projection of the first end portion on the base substrate and an orthographic projections of the first electrode of the fourth transistor on the base substrate.

11 . The display substrate according to the claim 10 , wherein at least part of the first electrode of the fourth transistor and the first end portion are arranged along the second direction.

12

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Zhang Tiaomei
• Yi Hong
• Gu Quanyong
• Li De
• Li Zhengkun
• Liu Guo

Classifications

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title