Display substrate and manufacturing method therefor, and display device

Patent metadata

Field	Value
Publication number	US-12579939-B2
Application number	US-202418992202-A
Country	US
Kind code	B2
Filing date	Apr 18, 2024
Priority date	May 17, 2023
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A display substrate includes a plurality of circuit units. Each circuit unit includes a pixel driving circuit. The pixel driving circuit at least includes a first transistor, a second transistor, a third transistor, a fourth transistor, a ninth transistor, a first storage capacitor and a second storage capacitor. A second electrode of the first transistor is connected to a first electrode of the second transistor, the gate electrode of the third transistor, and a first end of the first storage capacitor, respectively. A second electrode of the fourth transistor is connected to a second electrode of the ninth transistor, a second end of the first storage capacitor, and a second end of the second storage capacitor, respectively.

First claim

The invention claimed is:

1 . A display substrate, comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, wherein
at least one circuit unit comprises a pixel driving circuit, the pixel driving circuit at least comprises a first transistor as an initialization transistor, a second transistor as a compensation transistor, a third transistor as a driving transistor, a fourth transistor as a data writing transistor, a ninth transistor as a reference transistor, a first storage capacitor, and a second storage capacitor; a first electrode of the first transistor is connected to a first initial signal line, a second electrode of the first transistor is connected to a first electrode of the second transistor, a gate electrode of the third transistor, and a first end of the first storage capacitor; a first electrode of the fourth transistor is connected to a data signal line, a second electrode of the fourth transistor is connected to a second electrode of the ninth transistor, a second end of the first storage capacitor, and a second end of the second storage capacitor; a first electrode of the ninth transistor is connected to a first reference signal line; a first end of the second storage capacitor is connected to a first power supply line; and the first transistor, the second transistor, the fourth transistor, and the ninth transistor are oxide transistors, and the third transistor is a low-temperature polycrystalline silicon transistor.

2 . The display substrate according to claim 1 , wherein
the first transistor at least comprises a first top gate electrode and a first bottom gate electrode, an orthographic projection of the first top gate electrode on a plane of the display substrate at least partially overlaps with an orthographic projection of the first bottom gate electrode on the plane of the display substrate; and the first top gate electrode is in a shape of a strip extending in a unit row direction, and the first electrode of the first transistor and the second electrode of the first transistor are located on two sides of the first top gate electrode in a unit column direction.

3 . The display substrate according to claim 1 , wherein
the second transistor at least comprises a second top gate electrode and a second bottom gate electrode, an orthographic projection of the second top gate electrode on the plane of the display substrate at least partially overlaps with an orthographic projection of the second bottom gate electrode on the plane of the display substrate; and the second top gate electrode is in a shape of a strip extending in the unit column direction, and the first electrode of the second transistor and a second electrode of the second transistor are located on two sides of the second top gate electrode in the unit row direction.

4 . The display substrate according to claim 3 , wherein
the display substrate further comprises a fifth scan signal line and a fifth scan connection line, the second top gate electrode is connected to the fifth scan signal line, the second bottom gate electrode is connected to the fifth scan connection line, an orthographic projection of the fifth scan signal line on the plane of the display substrate at least partially overlaps with an orthographic projection of the fifth scan connection line on the plane of the display substrate, and the fifth scan signal line is connected to the fifth scan connection line through a via to form a scan signal line having a double-layer structure.

5 . The display substrate according to claim 1 , wherein
the fourth transistor at least comprises a fourth top gate electrode and a fourth bottom gate electrode, an orthographic projection of the fourth top gate electrode on the plane of the display substrate at least partially overlaps with an orthographic projection of the fourth bottom gate electrode on the plane of the display substrate; and the fourth top gate electrode is in a shape of a strip extending in the unit column direction, and the first electrode of the fourth transistor and the second electrode of the fourth transistor are located on two sides of the fourth top gate electrode in the unit row direction.

6 . The display substrate according to claim 1 , wherein
the ninth transistor at least comprises a ninth top gate electrode and a ninth bottom gate electrode, an orthographic projection of the ninth top gate electrode on the plane of the display substrate at least partially overlaps with an orthographic projection of the ninth bottom gate electrode on the plane of the display substrate; the ninth top gate electrode is in a shape of a strip extending in the unit column direction, and the first electrode of the ninth transistor and the second electrode of the ninth transistor are located on two sides of the ninth top gate electrode in the unit row direction.

7 . The display substrate according to claim 6 , wherein
the display substrate further comprises a second scan signal line and a second scan connection line, the ninth top gate electrode is connected to the second scan signal line, the ninth bottom gate electrode is connected to the second scan connection line, an orthographic projection of the second scan signal line on the plane of the display substrate at least partially overlaps with an orthographic projection of the second scan connection line on the plane of the display substrate, and the second scan signal line is connected to the second scan connection line through a via to form a scan signal line having a double-layer structure.

8 . The display substrate according to claim 1 , wherein a channel region of the fourth transistor and a channel region of the ninth transistor are on a same straight line extending in the unit row direction.

9 . The display substrate according to claim 1 , wherein
the first storage capacitor at least comprises a first electrode plate and a third electrode plate, an orthographic projection of the first electrode plate on the plane of the display substrate at least partially overlaps with an orthographic projection of the third electrode plate on the plane of the display substrate; the second storage capacitor at least comprises a second electrode plate and a fourth electrode plate, an orthographic projection of the second electrode plate on the plane of the display substrate at least partially overlaps with an orthographic projection of the fourth electrode plate on the plane of the display substrate; and the first electrode plate serves as the gate electrode of the third transistor, the second electrode plate is connected to the third electrode plate, and the fourth electrode plate is connected to the first power supply line.

10 . The display substrate according to claim 9 , wherein
in a direction perpendicular to the display substrate, at least one circuit unit comprises a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer that are sequentially disposed on a base substrate in a direction away from the base substrate; the first electrode plate and the second electrode plate are disposed in the first conductive layer, the third electrode plate and the fourth electrode plate are disposed in the second conductive layer, the second electrode plate is connected to the third electrode plate through a connection electrode disposed in the fourth conductive layer, and the first power supply line is disposed in the fifth conductive layer.

11 . The display substrate according to claim 10 , wherein
an electrode plate connection line is provided on a side of the fourth electrode plate in the unit row di

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Zhang Tiaomei
• Gao Wenhui
• Liu Lang
• Ma Hongbo
• Wu Jianpeng

Classifications

• G09G2330/10

  Dealing with defective pixels · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title