Pixel circuit having a node control sub-circuit, driving method therefor, display substrate, and display apparatus

Patent metadata

Field	Value
Publication number	US-12579935-B2
Application number	US-202218691051-A
Country	US
Kind code	B2
Filing date	Sep 29, 2022
Priority date	Sep 29, 2022
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A pixel circuit, a driving method therefor, a display substrate and a display apparatus, the pixel circuit includes a node control sub-circuit, a storage sub-circuit, a driving sub-circuit and a light emitting control sub-circuit; the storage sub-circuit is electrically connected to a second node and a first power supply line respectively, and is configured to charge the second node when a first scanning signal line is an effective level signal.

First claim

The invention claimed is:

1 . A pixel circuit configured to drive a light emitting device to emit light, comprising: a node control sub-circuit, a storage sub-circuit, a driving sub-circuit, and a light emitting control sub-circuit;
the node control sub-circuit is electrically connected to a first node, a second node, a third node, a fourth node, a first scanning signal line, a second scanning signal line, a first initial signal line, a second initial signal line, a reset signal line, a data signal line and a first power supply line respectively, and is configured to provide a signal of the first initial signal line or the third node to the first node, provide a signal of the second initial signal line to the fourth node and provide a signal of the data signal line to the second node under control of the reset signal line, the first scanning signal line and the second scanning signal line; the storage sub-circuit is electrically connected to the second node and the first power supply line respectively, and is configured to charge the second node when a signal of the first scanning signal line is an effective level signal; the driving sub-circuit is connected to the first node, the second node, and the third node respectively, and is configured to provide a drive current to the third node under control of the first node and the second node; the light emitting control sub-circuit is electrically connected to a light emitting signal line, the first power supply line, the second node, the third node, and the fourth node respectively, and is configured to provide a signal of the first power supply line to the second node and provide the signal of the third node to the fourth node under control of the light emitting signal line; and a first electrode of the light emitting device is connected to the fourth node, and a second electrode of the light emitting device is connected to a second power supply line, wherein the node control sub-circuit comprises: a first transistor and a second transistor, and, wherein the node control sub-circuit further comprises a first capacitor and the storage sub-circuit comprises a second capacitor, a second plate of the second capacitor comprises: a capacitor main body portion and a first connection block; the first connection block is connected to the capacitor main body portion, an orthographic projection of the capacitor main body portion on the base substrate at least partially overlaps with an orthographic projection of a first plate of the second capacitor on the base substrate, an orthographic projection of the first connection block on the base substrate partially overlaps with an orthographic projection of an active layer of the second transistor between control electrodes of the second transistor on the base substrate.

2 . The pixel circuit according to claim 1 , wherein a time period in which a signal of the reset signal line is an effective level signal comprises a first time period and a second time period, and the first time period occurs before the second time period;
a time period in which the signal of the first scanning signal line is an effective level signal comprises a third time period and a fourth time period, and the third time period occurs before the fourth time period; a time period in which a signal of the second scanning signal line is an effective level signal comprises a fifth time period and a sixth time period, the fifth time period occurs before the sixth time period, the second time period and the third time period at least partially overlap, and the fourth time period and the fifth time period at least partially overlap; and when the signals of the reset signal line, the first scanning signal line and the second scanning signal line are effective level signals, a signal of the light emitting signal line is an ineffective level signal, and when the signal of the light emitting signal line is an effective level signals, the signals of the reset signal line, the first scanning signal line and the second scanning signal line are ineffective level signals.

3 . The pixel circuit according to claim 1 , wherein the node control sub-circuit comprises: a reset sub-circuit, a write sub-circuit, a compensation sub-circuit, and an energy storage sub-circuit;
the reset sub-circuit is electrically connected to the reset signal line, the first initial signal line, the second initial signal line, the first node and the fourth node respectively, and is configured to provide the signal of the first initial signal line to the first node and provide the signal of the second initial signal line to the fourth node under the control of the reset signal line; the write sub-circuit is electrically connected to the first scanning signal line, the data signal line, and the second node respectively, and is configured to provide the signal of the data signal line to the second node under control of the first scanning signal line; the compensation sub-circuit is electrically connected to the second scanning signal line, the first node and the third node respectively, and is configured to provide the signal of the third node to the first node under control of the second scanning signal line; and the energy storage sub-circuit is electrically connected to the first node and the first power supply line respectively, and is configured to store a voltage difference of a signal between the first node and the first power supply line.

4 . The pixel circuit according to claim 3 , wherein the reset sub-circuit is further connected to the first scanning signal line and is configured to provide the signal of the first initial signal line to the first node and provide the signal of the second initial signal line to the fourth node under control of the reset signal line and the first scanning signal line.

5 . The pixel circuit according to claim 4 , wherein the reset sub-circuit comprises the first transistor, a seventh transistor, and an eighth transistor, the write sub-circuit comprises a fourth transistor, and the compensation sub-circuit comprises: the second transistor, and the energy storage sub-circuit comprises: the first capacitor;
a control electrode of the first transistor is electrically connected to the reset signal line, a first electrode of the first transistor is electrically connected to the first initial signal line, and a second electrode of the first transistor is electrically connected to a first electrode of the eighth transistor; a control electrode of the second transistor is electrically connected to the second scanning signal line, a first electrode of the second transistor is electrically connected to the first node, and a second electrode of the second transistor is electrically connected to the third node; a control electrode of the fourth transistor is electrically connected to the first scanning signal line, a first electrode of the fourth transistor is electrically connected to the data signal line, and a second electrode of the fourth transistor is electrically connected to the second node; a control electrode of the seventh transistor is electrically connected to the reset signal line, a first electrode of the seventh transistor is electrically connected to the second initial signal line, and a second electrode of the seventh transistor is electrically connected to the fourth node; a control electrode of the eighth transistor is electrically connected to the first scanning signal line, and a second electrode of the eighth transistor is electrically connected to the first node; and one end of the first capacitor is electrically connected to the first node, and the other end of the first capacitor is electrically connected to the first power supply line.

6 . The pixel circuit according to claim 3 , wherein the reset sub-circuit

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Zhao Pan
• Qing Haigang
• Yu Ziyang
• Jiang Zhiliang
• Wang Miao
• Hu Ming
• Zhang Tiaomei

Classifications

• G09G3/34

  by control of light from an independent source · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G2340/0435

  Change or adaptation of the frame rate of the video stream · CPC title

• G09G2330/023

  using energy recovery or conservation · CPC title

• G09G2320/0252

  Improving the response speed · CPC title