Display device and electronic device having the same

Patent metadata

Field	Value
Publication number	US-12579928-B2
Application number	US-202418672078-A
Country	US
Kind code	B2
Filing date	May 23, 2024
Priority date	Sep 19, 2023
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A display device includes: a display panel; a first light emitting driving circuit to provide first emission signals; and a second light emitting driving circuit to provide second emission signals. The display panel includes: a plurality of pixels, each including a first light emitting element and a second light emitting element; and a light control pattern overlapping with the second light emitting element of each of the plurality of pixels in a plan view. Each of the plurality of pixels is to emit light through the first light emitting element when a corresponding first emission signal is at an active level, and emit light through the second light emitting element when a corresponding second emission signal is at the active level. A part of the first emission signals and the second emission signals remains at an inactive level during at least one frame based on an operating mode.

First claim

What is claimed is:

1 . A display device comprising:
a display panel; a first light emitting driving circuit configured to provide first emission signals; and a second light emitting driving circuit configured to provide second emission signals, wherein the display panel comprises:
a plurality of pixels, each comprising a first light emitting element and a second light emitting element; and
a light control pattern overlapping with the second light emitting element of each of the plurality of pixels in a plan view,
wherein each of the plurality of pixels is configured to emit light through the first light emitting element when a corresponding first emission signal from among the first emission signals is at an active level, and emit light through the second light emitting element when a corresponding second emission signal from among the second emission signals is at the active level, wherein the first light emitting element of each of the plurality of pixels is configured to not emit light when the corresponding first emission signal is at an inactive level, and the second light emitting element of each of the plurality of pixels is configured to not emit light when the corresponding second emission signal is at the inactive level, and wherein a part of the first emission signals and the second emission signals remains at the inactive level during at least one frame based on an operating mode.

2 . The display device of claim 1 , wherein the display panel comprises a first display area and a second display area, and
wherein, in a first operating mode, the first light emitting driving circuit is configured to sequentially transition the first emission signals to the active level, and the second light emitting driving circuit is configured to sequentially transition the second emission signals to the active level.

3 . The display device of claim 2 , wherein a second operating mode comprises a first period in which the first display area is operated, and a second period in which the second display area is operated,
wherein, during the first period, the first light emitting driving circuit is configured to maintain first emission signals corresponding to the first display area from among the first emission signals at the inactive level, and the second light emitting driving circuit is configured to sequentially transition second emission signals corresponding to the first display area from among the second emission signals to the active level, and wherein, during the second period, the first light emitting driving circuit is configured to sequentially transition first emission signals corresponding to the second display area from among the first emission signals to the active level, and the second light emitting driving circuit is configured to sequentially transition second emission signals corresponding to the second display area from among the second emission signals to the active level.

4 . The display device of claim 2 , wherein a third operating mode comprises a first period in which the first display area is operated, and a second period in which the second display area is operated,
wherein, during the first period, the first light emitting driving circuit is configured to sequentially transition first emission signals corresponding to the first display area from among the first emission signals to the active level, and the second light emitting driving circuit is configured to maintain second emission signals corresponding to the first display area from among the second emission signals at the inactive level, and wherein, during the second period the first light emitting driving circuit is configured to maintain first emission signals corresponding to the second display area from among the first emission signals at the inactive level, and the second light emitting driving circuit is configured to sequentially transition second emission signals corresponding to the second display area from among the second emission signals to the active level.

5 . The display device of claim 1 , wherein the first light emitting driving circuit comprises a plurality of stages, each configured to receive clock signals and a carry signal, and output a corresponding signal from among the first emission signals.

6 . The display device of claim 5 , wherein each of the plurality of stages comprises:
an input enable circuit configured to output the carry signal to a carry input node in response to a first enable signal, and output a first voltage to the carry input node in response to a second enable signal; and a driving circuit configured to output the corresponding signal from among the first emission signals in response to a signal of the carry input node.

7 . The display device of claim 6 , wherein the input enable circuit comprises:
a first transistor connected between the carry input node and an input terminal configured to receive the carry signal, the first transistor comprising a gate electrode configured to receive the first enable signal; and a second transistor connected between the carry input node and a first voltage terminal configured to receive the first voltage, the second transistor comprising a gate electrode configured to receive the second enable signal.

8 . The display device of claim 7 , wherein, in a first operating mode, each of the first transistor and the second transistor is configured to be turned off, and
wherein, in a second operating mode, each of the first transistor and the second transistor is configured to be turned on.

9 . The display device of claim 7 , wherein the input enable circuit further comprises:
a third transistor connected between the carry input node and a second voltage terminal configured to receive a second voltage, the third transistor comprising a gate electrode configured to receive a third enable signal.

10 . The display device of claim 1 , wherein the display panel comprises a first display area, a second display area, and a third display area, and
wherein the first and second light emitting driving circuits are configured to maintain a part of the first emission signals and the second emission signals at the inactive level when at least one of the first display area, the second display area, or the third display area remains at the inactive level based on the operating mode.

11 . The display device of claim 1 , wherein the light control pattern comprises a plurality of patterns, each extending in a first direction and spaced from one another in a second direction.

12 . The display device of claim 1 , further comprising:
a plurality of scan lines connected to the plurality of pixels; and a scan driving circuit configured to provide scan signals to the plurality of scan lines.

13 . The display device of claim 12 , wherein each of the plurality of pixels comprises:
a first transistor connected between a first driving voltage line and a first node, and comprising a gate electrode connected to a second node; a second transistor connected between a data line and the second node, and comprising a gate electrode connected to a corresponding one of the plurality of scan lines; a third transistor connected between the first node and an anode of the first light emitting element, and comprising a gate electrode configured to receive a corresponding signal from among the first emission signals; and a fourth transistor connected between the first node and an anode of the second light emitting element, and comprising a gate electrode configured to receive a corresponding signal from among the second emission signals.

14 . A display device comprising:
a

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Junwon

Classifications

• G09G2330/023

  using energy recovery or conservation · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2310/06

  Details of flat display driving waveforms · CPC title

• G09G2354/00

  Aspects of interface with display user · CPC title

• G09G2380/10

  Automotive applications · CPC title