Method and system for transmitting data, timing controller, and source driver chip

Patent metadata

Field	Value
Publication number	US-12579925-B2
Application number	US-202418898425-A
Country	US
Kind code	B2
Filing date	Sep 26, 2024
Priority date	May 30, 2022
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

Provided is a method for transmitting data. The method includes: transmitting equalization matching data to a source driver chip upon sending a link stable pattern to the source driver chip, wherein the equalization matching data is configured for the source driver chip to determine a target equalization gain, and perform gain compensation, based on the target equalization gain, on display data from the timing controller; and transmitting the display data to the source driver chip in response to a first condition being met, wherein the first condition is that the source driver chip determines the target equalization gain. Prior to transmitting the equalization matching data to the source driver chip upon sending the link stable pattern to the source driver chip, the method further includes transmitting equalization gain configuration information to the source driver chip.

First claim

What is claimed is:

1 . A method for transmitting data, applicable to a timing controller, the method comprising:
transmitting equalization matching data to a source driver chip upon sending a link stable pattern to the source driver chip, wherein the equalization matching data is configured for the source driver chip to determine a target equalization gain, and perform gain compensation, based on the target equalization gain, on display data from the timing controller; and transmitting the display data to the source driver chip in response to a first condition being met, wherein the first condition is that the source driver chip determines the target equalization gain; wherein prior to transmitting the equalization matching data to the source driver chip upon sending the link stable pattern to the source driver chip, the method further comprises: transmitting equalization gain configuration information to the source driver chip, so that the source driver chip is capable of: determining a plurality of reference equalization gains based on the equalization gain configuration information; acquiring, after receiving the equalization matching data from the timing controller, a plurality of gain compensated equalization matching data by performing gain compensation on the equalization matching data based on the plurality of reference equalization gains; determining error rates of the plurality of gain compensated equalization matching data; and determining the target equalization gain from the plurality of reference equalization gains based on the error rates of the plurality of gain compensated equalization matching data.

2 . The method according to claim 1 , wherein a number of clock edges in a unit time in a signal for carrying the equalization matching data is greater than a number of clock edges in the unit time in a signal for carrying the link stable pattern, and the number of the clock edges in the unit time in the signal for carrying the link stable pattern is greater than a number of clock edges in the unit time in a signal for carrying clock calibration data, wherein the clock calibration data is transmitted, prior to transmitting the link stable pattern, by the timing controller to the source driver chip.

3 . The method according to claim 1 , wherein the equalization matching data is transmitted by the timing controller upon being powered on or reset prior to transmitting the display data to the source driver chip.

4 . The method according to claim 2 , wherein the equalization matching data is transmitted by the timing controller upon being powered on or reset prior to transmitting the display data to the source driver chip.

5 . The method according to claim 1 , wherein the equalization matching data is transmitted each time the timing controller transmits M frames of display data to the source driver chip, wherein M is an integer greater than 0.

6 . The method according to claim 2 , wherein the equalization matching data is transmitted each time the timing controller transmits M frames of display data to the source driver chip, wherein M is an integer greater than 0.

7 . The method according to claim 3 , wherein the equalization matching data is transmitted each time the timing controller transmits M frames of display data to the source driver chip, wherein M is an integer greater than 0.

8 . The method according to claim 1 , wherein
prior to transmitting the equalization matching data to the source driver chip, the method further comprises:
sending a first control instruction to the source driver chip, wherein the first control instruction instructs the source driver chip to perform automatic equalization; and/or
upon transmitting the equalization matching data to the source driver chip, the method further comprises:
sending a second control instruction to the source driver chip, wherein the second control instruction indicates completion of transmission of the equalization matching data.

9 . The method according to claim 1 , further comprising:
sending, upon transmitting clock calibration data to the source driver chip, configuration information to the source driver chip over a data channel, wherein the configuration information is provided for the source driver chip to configure a physical layer parameter.

10 . A method for transmitting data, applicable to a source driver chip, the method comprising:
receiving equalization matching data from a timing controller upon receiving a link stable pattern; determining a target equalization gain by performing automatic equalization based on the equalization matching data; receiving display data from the timing controller; and performing gain compensation on the display data based on the target equalization gain; wherein determining the target equalization gain by performing the automatic equalization based on the equalization matching data, comprises: receiving equalization gain configuration information from the timing controller; determining a plurality of reference equalization gains based on the equalization gain configuration information; acquiring a plurality of gain compensated equalization matching data by performing gain compensation on the equalization matching data based on the plurality of reference equalization gains; determining error rates of the plurality of gain compensated equalization matching data; and determining the target equalization gain from the plurality of reference equalization gains based on the error rates of the plurality of gain compensated equalization matching data.

11 . The method according to claim 10 , wherein a number of clock edges in a unit time in a signal for carrying the equalization matching data is greater than a number of clock edges in the unit time in a signal for carrying the link stable pattern, and the number of the clock edges in the unit time in the signal for carrying the link stable pattern is greater than a number of clock edges in the unit time in a signal for carrying clock calibration data, wherein the clock calibration data is received by the source driver chip prior to receiving the link stable pattern;
and, determining the target equalization gain by performing automatic equalization based on the equalization matching data comprises: acquiring a plurality of gain compensated equalization matching data by performing gain compensation on the equalization matching data based on a plurality of reference equalization gains; determining error rates of the plurality of gain compensated equalization matching data; and determining the target equalization gain from the plurality of reference equalization gains based on the error rates of the plurality of gain compensated equalization matching data.

12 . The method according to claim 10 , further comprising:
receiving, upon receiving clock calibration data, configuration information from the timing controller over a data channel, wherein the configuration information is provided for the source driver chip to configure a physical layer parameter.

13 . A timing controller, comprising: a processor, a transceiver, and a memory; wherein
the memory stores one or more instructions executable by the processor; and the processor, when loading and executing the one or more instructions, is caused to control the transceiver to perform the method as defined in claim 1 .

14 . The timing controller according to claim 13 , wherein a number of clock edges in a unit time in a signal for carrying the equalization matching data is greater than a number of clock edges in the unit time in a signal for carrying the link stable pattern, and t

Assignees

• Beijing Eswin Computing Tech Co Ltd
• Hefei Eswin Computing Tech Co Ltd

Inventors

• Nam Jangjin
• Lee Dongmyung
• Baek Donghoon
• Lee Daejoon

Classifications

• G09G2370/08

  Details of image data interface between the display device controller and the data line driver circuit · CPC title

• G09G2330/026

  Arrangements or methods related to booting a display · CPC title

• G09G2320/0693

  Calibration of display systems · CPC title

• G09G2370/10

  Use of a protocol of communication by packets in interfaces along the display data pipeline · CPC title

• G09G2370/04

  Exchange of auxiliary data, i.e. other than image data, between monitor and graphics controller · CPC title