Methods, devices and systems with authenticated memory device access transactions

Patent metadata

Field	Value
Publication number	US-12579246-B2
Application number	US-202318144013-A
Country	US
Kind code	B2
Filing date	May 5, 2023
Priority date	Dec 2, 2022
Publication date	Mar 17, 2026
Grant date	Mar 17, 2026

Abstract

A method can include determining the CS signal has transitioned from inactive to active and receiving at least target address information at a bus interface of the IC device. In response to target address information, retrieving data stored at a corresponding storage location of the IC device. By operation of authentication circuits, generating an authentication value using at least one cryptographic function that includes at least the authentication parameters and the retrieved data. The authentication value can be transmitted with retrieved data from the IC device. Corresponding devices and systems are also disclosed.

First claim

What is claimed is:

1 . A method, comprising:
receiving a chip select (CS) signal at an integrated circuit (IC) device; determining the CS signal has transitioned from inactive to active; receiving at least target address information at a bus interface of the IC device; in response to the target address information, retrieving data stored at a corresponding storage location of the IC device; by operation of authentication circuits of the IC device, generating an authentication value with at least one cryptographic function using at least the authentication parameters and the retrieved data; and transmitting the authentication value with the retrieved data from the IC device; wherein the CS signal remains active while receiving the target address, retrieving the data, generating the authentication value, and transmitting the authentication value and retrieved data.

2 . The method of claim 1 , further including:
by operation of the authentication circuits, encrypting the retrieved data to generate encrypted data; and the retrieved data output with the authentication value are the encrypted data.

3 . The method of claim 1 , wherein:
the IC device comprises at least one memory cell array; and the storage location is at least one of a plurality of storage locations in the memory cell array.

4 . The method of claim 1 , wherein:
the IC device comprises a plurality of registers; and the storage location is at least one of the registers.

5 . The method of claim 1 , further including:
receiving a command with the target address information at the bus interface, the command identifying an operation to be executed by the IC device; and the command being received while the CS signal remains active.

6 . The method of claim 1 , wherein:
transmitting the authentication value with the retrieved data from the IC device is selected from the group of: transmitting from the bus interface and transmitting over data outputs different than the bus interface.

7 . The method of claim 1 , further including:
by operation of a host device,
transitioning the CS signal from inactive to active,
receiving the retrieved data and authentication value from the IC device,
using at least the authentication parameters and authentication value to authenticate the retrieved data, and
executing processor functions using the authenticated retrieved data.

8 . The method of claim 1 , wherein:
the authentication value output with the retrieved data has an order selected from the group of: being output after the retrieved data, being output prior to the retrieved data, and being output interspersed with the retrieved data.

9 . A device, comprising:
storage circuits configured to store authentication parameters and data; control circuits configured to, while a chip select (CS) signal remains asserted active, retrieve data stored at a location in the device indicated by target address information; authentication circuits configured to, while the CS signal remains asserted active, generate an authentication value with at least one cryptographic function that uses the authentication parameters and the retrieved data; and a bus interface circuit configured to
receive the CS signal and target address information, and
while the CS signal remains asserted active, transmit the authentication value with the retrieved data; wherein
the storage circuits, control circuits, authentication circuits, and bus interface circuits are formed with a same integrated circuit (IC) substrate.

10 . The device of claim 9 , wherein:
the authentication circuits are further configured to, while the CS signal remains asserted active, encrypt the retrieved data to generate encrypted data; and the bus interface circuit is configured to, while the CS signal remains asserted active, transmit the authentication value with the encrypted data.

11 . The device of claim 9 , wherein:
the storage circuits comprise a memory cell array; and the data are stored in the memory cell array.

12 . The device of claim 9 , wherein:
the storage circuits comprise a plurality of registers; and the data are stored in at least one of the registers.

13 . The device of claim 9 , wherein the bus interface is further configured to receive command information with the address information while the CS signal remains asserted active.

14 . The device of claim 9 , wherein:
the bus interface circuits are further configured to transmit the authentication value with respect to the retrieved data in an order selected from the group of: being output after the retrieved data, being output prior to the retrieved data, and being output interspersed with the retrieved data.

15 . A system, comprising:
an integrated circuit (IC) device that includes
storage circuits configured to store authentication parameters and data,
control circuits configured to, while a chip select (CS) signal remains asserted active, retrieve data stored at a location in the device indicated by target address information, and
authentication circuits configured to, while the CS signal remains asserted active, generate an authentication value with at least one cryptographic function using at least the authentication parameters and the retrieved data; and
a bus system configured to, while the CS signal remains asserted active,
transmit at least the target address information and the CS signal to the IC device, and
transmit the authentication value and retrieved data from the IC device.

16 . The system of claim 15 , wherein:
the authentication circuits are further configured to, while the CS signal remains asserted active, encrypt the retrieved data to generate encrypted data; and the bus system is configured to, while the CS signal remains asserted active, transmit the authentication value with the encrypted data.

17 . The system of claim 15 , further including:
a host device coupled to the bus system and configured to
assert the CS signal active, and
transmit at least the target address information to the IC device.

18 . The system of claim 17 , wherein:
the host device includes host authentication circuits configured to authenticate retrieved data received from the IC device using the authentication parameters.

19 . The system of claim 18 , wherein:
the host authentication circuits comprise an Ascon type authenticated cipher.

20 . The system of claim 17 , wherein:
the host device includes at least one processor configured to execute functions with retrieved data that is authenticated by the host authentication circuits.

Assignees

• Infineon Technologies LLC

Inventors

• Zitlaw Clifford
• Yogev Yoav
• Hasan Qamrul

Classifications

• G06F21/72

  in cryptographic circuits · CPC title

• G06F21/602

  Providing cryptographic facilities or services · CPC title

• G06F21/44 Primary

  Program or device authentication · CPC title