Metal foil with carrier and use method and manufacturing method therefor

Patent metadata

Field	Value
Publication number	US-12575370-B2
Application number	US-202017612041-A
Country	US
Kind code	B2
Filing date	May 18, 2020
Priority date	May 20, 2019
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

Provided is a carrier-attached metal foil with which both exposure for rough circuits and exposure for fine circuits in wiring formation can be performed based on the same alignment marks, and as a result, rough circuits and fine circuits can be simultaneously formed in a one-stage circuit formation process. This carrier-attached metal foil is a carrier-attached metal foil including a carrier, a release layer provided on at least one surface of the carrier, and a metal layer provided on the release layer, wherein the carrier-attached metal foil includes: a wiring region throughout which the carrier, the release layer, and the metal layer are present; and at least two positioning regions provided on the at least one surface of the carrier-attached metal foil and forming alignment marks used for positioning in wiring formation involving exposure and development.

First claim

The invention claimed is:

1 . A carrier-attached metal foil comprising a carrier, a release layer provided on at least one surface of the carrier, and a metal layer provided on the release layer, wherein the carrier-attached metal foil comprises:
a wiring region throughout which the carrier, the release layer, and the metal layer are present; and at least two positioning regions provided on the at least one surface of the carrier-attached metal foil, wherein the at least two positioning regions are defined by depressed portions recessed into and integral with the carrier, thereby forming alignment marks used for positioning in wiring formation involving exposure and development.

2 . The carrier-attached metal foil according to claim 1 , wherein the alignment marks have at least one shape selected from the group consisting of a circle, a cross, and polygons.

3 . The carrier-attached metal foil according to claim 1 , wherein each of the depressed portions has a maximum depth of 0.1 μm or more and 1000 μm or less.

4 . The carrier-attached metal foil according to claim 1 , wherein each of the depressed portions has a planar view shape of a circle having an outer diameter of 50 μm or more and 5000 μm or less.

5 . The carrier-attached metal foil according to claim 1 , wherein an angle formed by a major surface of the carrier and a tangent to an inner wall surface of each of the depressed portions is 40° or more.

6 . The carrier-attached metal foil according to claim 1 , wherein each of the depressed portions has a round open end, and the round open end has a radius of curvature of 100 μm or less.

7 . The carrier-attached metal foil according to claim 1 , having 200 or less of the alignment marks.

8 . The carrier-attached metal foil according to claim 1 , wherein the carrier is composed of glass or ceramic.

9 . A method for forming wiring through exposure and development using the carrier-attached metal foil according to claim 1 , comprising performing positioning based on the positioning regions of the carrier-attached metal foil prior to exposure,
wherein exposures for circuits having different circuit widths are separately performed, and development for the circuits is simultaneously performed.

10 . The method according to claim 9 , the method for forming wiring being a method for forming a redistribution layer, wherein the circuits has a fine circuit having a circuit width of 0.1 μm or more and 5 μm or less, and a rough circuit having a circuit width of greater than 5 μm and 500 μm or less.

11 . The method according to claim 10 , wherein R/F representing a ratio of a maximum circuit width of the rough circuit, R, to a minimum circuit width of the fine circuit, F, is 2.0 or more and 500 or less.

12 . A method for manufacturing the carrier-attached metal foil according to claim 1 , comprising:
providing a carrier; processing predetermined regions of at least one surface of the carrier to form at least two processed portions constituting the alignment marks, thereby defining the at least two positioning regions; and forming the release layer and the metal layer in sequence on the at least one surface of the carrier.

13 . The method according to claim 12 , wherein formation of the alignment marks is performed using at least one method selected from an etching method, a blasting method, and a laser ablation method.

Assignees

• Mitsui Mining & Smelting Co Ltd
• Mitsui Kinzoku Company Ltd

Inventors

• Matsuura Yoshinori
• Nakamura Toshimi

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W70/05 Primary

  of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

• H05K3/4682

  Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil · CPC title

• H05K3/4679

  Aligning added circuit layers or via connections relative to previous circuit layers · CPC title

• H10W46/00

  Marks applied to devices, e.g. for alignment or identification · CPC title