Display panel

Patent metadata

Field	Value
Publication number	US-12575296-B2
Application number	US-202318362054-A
Country	US
Kind code	B2
Filing date	Jul 31, 2023
Priority date	Dec 2, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

The present application provides a display panel including: a substrate, a thin film transistor layer, an insulation layer, an anode layer, an electron transport layer, and a cathode layer. The thin film transistor layer includes an auxiliary transistor. A first cathode auxiliary hole is defined in the insulation layer. The anode layer includes a connection portion disposed in the first cathode auxiliary hole and electrically connected to the auxiliary transistor. The electron transport layer includes an electron transport portion disposed to correspond to the connection portion. The cathode layer includes a cathode auxiliary electrode connected to the electron transport portion. The present application can prevent an issue of uneven brightness due to voltage decrease and improves quality of the display panel.

First claim

What is claimed is:

1 . A display panel, comprising:
a substrate; a thin film transistor layer disposed on the substrate and comprising an auxiliary transistor; an insulation layer disposed on a side of the thin film transistor layer away from the substrate, wherein a first cathode auxiliary hole is defined in the insulation layer; an anode layer disposed on a side of the insulation layer away from the substrate and comprising a connection portion disposed in the first cathode auxiliary hole and electrically connected to the auxiliary transistor; an electron transport layer disposed on a side of the anode layer away from the substrate and comprising an electron transport portion disposed to correspond to the connection portion; and a cathode layer disposed on a side of the electron transport layer away from the substrate and comprising a cathode auxiliary electrode electrically connected to the electron transport portion.

2 . The display panel according to claim 1 , wherein the display panel further comprises a pixel definition layer disposed between the anode layer and the electron transport layer, a second cathode auxiliary hole is defined in the pixel definition layer, the second cathode auxiliary hole is defined to correspond to the first cathode auxiliary hole, and the electron transport portion is disposed in the second cathode auxiliary hole.

3 . The display panel according to claim 1 , wherein the connection portion comprises a first sub-electrode portion and a second sub-electrode portion;
the first sub-electrode portion is connected to one of a source electrode and a drain electrode of the auxiliary transistor; the second sub-electrode portion is disposed circularly on a sidewall of the first cathode auxiliary hole and is connected to the first sub-electrode portion.

4 . The display panel according to claim 3 , wherein the second sub-electrode portion covers the sidewall of the first cathode auxiliary hole.

5 . The display panel according to claim 1 , wherein an end portion of a side of the connection portion away from the substrate is flush with the insulation layer.

6 . The display panel according to claim 2 , wherein the electron transport portion comprises a first sub-transport portion and a second sub-transport portion;
the first sub-transport portion is disposed circularly in the first cathode auxiliary hole; the second sub-transport portion is disposed circularly in the second cathode auxiliary hole and is connected to the first sub-transport portion; and an orthographic projection of the connection portion on the substrate is within an orthographic projection of the electron transport portion on the substrate.

7 . The display panel according to claim 2 , wherein the electron transport portion covers the second cathode auxiliary hole.

8 . The display panel according to claim 7 , wherein the electron transport layer further comprises a third sub-transport portion disposed on a side of the pixel definition layer away from the substrate and connected to the electron transport portion.

9 . The display panel according to claim 1 , wherein the pixel definition layer further comprises a pixel definition portion disposed in the first cathode auxiliary hole and partially covering the connection portion.

10 . The display panel according to claim 9 , wherein an end portion of a side of the pixel definition portion away from the substrate is flush with an end portion of a side of the connection portion away from the substrate.

11 . The display panel according to claim 10 , wherein the end portion of the side of the pixel definition portion away from the substrate is flush with the insulation layer.

12 . A display panel, comprising:
a substrate; a thin film transistor layer disposed on the substrate and comprising an auxiliary transistor; an insulation layer disposed on a side of the thin film transistor layer away from the substrate, wherein a first cathode auxiliary hole is defined in the insulation layer; an anode layer disposed on a side of the insulation layer away from the substrate and comprising a connection portion disposed in the first cathode auxiliary hole and electrically connected to the auxiliary transistor; an electron transport layer disposed on a side of the anode layer away from the substrate and comprising an electron transport portion disposed to correspond to the connection portion; and a cathode layer disposed on a side of the electron transport layer away from the substrate and comprising a cathode auxiliary electrode electrically connected to the electron transport portion; wherein the display panel further comprises a pixel definition layer disposed between the anode layer and the electron transport layer, a second cathode auxiliary hole is defined in the pixel definition layer, the second cathode auxiliary hole is defined to correspond to the first cathode auxiliary hole, and the electron transport portion is disposed in the second cathode auxiliary hole; wherein the connection portion comprises a first sub-electrode portion and a second sub-electrode portion, the first sub-electrode portion is connected to one of a source electrode and a drain electrode of the auxiliary transistor, and the second sub-electrode portion is disposed circularly on a sidewall of the first cathode auxiliary hole and is connected to the first sub-electrode portion.

13 . The display panel according to claim 12 , wherein the second sub-electrode portion covers the sidewall of the first cathode auxiliary hole.

14 . The display panel according to claim 12 , wherein an end portion of a side of the connection portion away from the substrate is flush with the insulation layer.

15 . The display panel according to claim 12 , wherein the electron transport portion comprises a first sub-transport portion and a second sub-transport portion;
the first sub-transport portion is disposed circularly in the first cathode auxiliary hole; the second sub-transport portion is disposed circularly in the second cathode auxiliary hole and is connected to the first sub-transport portion; and an orthographic projection of the connection portion on the substrate is within an orthographic projection of the electron transport portion on the substrate.

16 . The display panel according to claim 12 , wherein the electron transport portion covers the second cathode auxiliary hole.

17 . The display panel according to claim 16 , wherein the electron transport layer further comprises a third sub-transport portion disposed on a side of the pixel definition layer away from the substrate and connected to the electron transport portion.

18 . The display panel according to claim 12 , wherein the pixel definition layer further comprises a pixel definition portion disposed in the first cathode auxiliary hole and partially covering the connection portion.

19 . The display panel according to claim 18 , wherein an end portion of a side of the pixel definition portion away from the substrate is flush with an end portion of a side of the connection portion away from the substrate.

20 . The display panel according to claim 19 , wherein the end portion of the side of the pixel definition portion away from the substrate is flush with the insulation layer.

Assignees

• Shenzhen China Star Optoelectronics Semiconductor Display Tech Co Ltd

Inventors

• Zhou Libin
• Qin Shijian
• Yuan Xialiang

Classifications

• H10K59/122 Primary

  Pixel-defining structures or layers, e.g. banks · CPC title

• H10K50/167

  between the light-emitting layer and the anode · CPC title

• H10K50/166

  comprising a multilayered structure · CPC title

• H10K59/80522 Primary

  combined with auxiliary electrodes · CPC title