Display substrate and display apparatus

US12575277B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12575277-B2
Application numberUS-202218033341-A
CountryUS
Kind codeB2
Filing dateJun 29, 2022
Priority dateJun 29, 2022
Publication dateMar 10, 2026
Grant dateMar 10, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A display substrate and a display apparatus. The display substrate includes an electrostatic discharge protection circuit, a power supply line, and at least one auxiliary electrode. The electrostatic discharge protection circuit includes multiple electrostatic discharge protection units, at least one of which extends along a first inclined direction, there is a first preset included angle between the first inclined direction and a first direction, the first direction is an extension direction of a scan signal line in the display region, the first preset included angle is greater than 0° and less than 90°; the first trace region includes the power supply line and at least one auxiliary electrode, an orthographic projection of the at least one auxiliary electrode on a display substrate plane is overlapped with that of the power supply line on the display substrate plane, the at least one auxiliary electrode is connected with the power supply line.

First claim

Opening claim text (preview).

The invention claimed is: 1 . A display substrate, comprising: a display region, and a non-display region located on a periphery of the display region, wherein the non-display region comprises a composite circuit region, and a first trace region located on a side of the composite circuit region away from the display region; the composite circuit region comprises an electrostatic discharge protection circuit, the electrostatic discharge protection circuit comprises a plurality of electrostatic discharge protection units, at least one electrostatic discharge protection unit in the plurality of electrostatic discharge protection units extends along a first inclined direction, there is a first preset included angle between the first inclined direction and a first direction, the first preset included angle is greater than 0° and less than 90°, and the first direction is an extension direction of a scan signal line in the display region; the first trace region comprises a power supply line and at least one auxiliary electrode, an orthographic projection of the at least one auxiliary electrode on a plane of the display substrate is overlapped with an orthographic projection of the power supply line on the plane of the display substrate, and the at least one auxiliary electrode is connected with the power supply line; wherein the non-display region further comprises a second trace region located on a side of the first trace region away from the display region, the non-display region further comprises a plurality of crack detection lines, a crack detection line is configured to detect a crack, the crack detection line comprises a detection connection line located in the composite circuit region, a detection lead line located in the first trace region, and a detection extension line located in the second trace region, which are sequentially connected. 2 . The display substrate according to claim 1 , wherein the non-display region comprises: a first voltage signal line, a second voltage signal line, and an electrostatic discharge protection line, each electrostatic discharge protection unit comprises at least two transistors in series, a first electrode of each transistor is connected with a gate electrode, the first voltage signal line is connected with a transistor at one end of the electrostatic discharge protection unit, the second voltage signal line is connected with another transistor at the other end of the electrostatic discharge protection unit, the electrostatic discharge protection line is connected with any one connection node located between the one transistor and the another transistor, and the electrostatic discharge protection unit is configured to discharge electrostatic charges accumulated on the electrostatic discharge protection line. 3 . The display substrate according to claim 1 , wherein the auxiliary electrode comprises a plurality of sub-auxiliary electrodes, which are sequentially and continuously disposed along an extension direction of the power supply line, and the plurality of sub-auxiliary electrodes are all disposed on a side of the detection lead line. 4 . The display substrate according to claim 1 , wherein the auxiliary electrode comprises a plurality of sub-auxiliary electrodes, the plurality of sub-auxiliary electrodes are sequentially disposed at intervals along an extension direction of the power supply line, the plurality of sub-auxiliary electrodes comprise at least one of the first sub-auxiliary electrode, the second sub-auxiliary electrode, and the third sub-auxiliary electrode, the first sub-auxiliary electrode is disposed on a side of the detection lead line in an opposite direction of the first direction, the second sub-auxiliary electrode is disposed between detection lead lines, and the third sub-auxiliary electrode is disposed on a side of the detection lead line in the first direction. 5 . The display substrate according to claim 1 , wherein the power supply line is located in the first trace region, an extension direction of the detection lead line intersects with an extension direction of the power supply line, and a film layer on which the auxiliary electrode is located, a film layer on which the detection lead line is located, and a film layer on which the power supply line is located, are located in different film layers. 6 . The display substrate according to claim 5 , wherein the auxiliary electrode comprises at least one of a first-type auxiliary electrode and a second-type auxiliary electrode, in a direction perpendicular to the plane of the display substrate, a film layer on which the first-type auxiliary electrode is located is between the film layer on which the detection lead line is located and the film layer on which the power supply line is located, and a film layer on which the second-type auxiliary electrode is located is on a side of the power supply line away from the film layer on which the detection lead line is located. 7 . The display substrate according to claim 6 , wherein an orthographic projection of the detection lead line on the plane of the display substrate is not overlapped with an orthographic projection of the first-type auxiliary electrode on the plane of the display substrate, and the orthographic projection of the detection lead line on the plane of the display substrate is overlapped with an orthographic projection of the second-type auxiliary electrode on the plane of the display substrate. 8 . The display substrate according to claim 6 , wherein in the direction perpendicular to the plane of the display substrate, the display substrate comprises a semiconductor layer, a first conductive layer, a second conductive layer, and a third conductive layer which are sequentially disposed on a base substrate; the semiconductor layer comprises active layers of at least two transistors; the first conductive layer comprises gate electrodes of the at least two transistors, and the detection lead line, the second conductive layer comprises the first-type auxiliary electrode; the third conductive layer comprises first electrodes of the at least two transistors, second electrodes of the at least two transistors, and the power supply line. 9 . The display substrate according to claim 8 , wherein the display substrate further comprises a fourth conductive layer disposed on a side of the third conductive layer away from the base substrate, and the fourth conductive layer comprises the second-type auxiliary electrode. 10 . The display substrate according to claim 1 , wherein the at least one electrostatic discharge protection unit extending along the first inclined direction comprises the at least two transistors in the at least one electrostatic discharge protection unit are sequentially disposed along the first inclined direction. 11 . The display substrate according to claim 1 , wherein the plurality of electrostatic discharge protection units are sequentially disposed along a second inclined direction, or the plurality of electrostatic discharge protection units are arranged in an array along the first inclined direction and the second inclined direction, and the second inclined direction intersects with the first inclined direction. 12 . The display substrate according to claim 2 , wherein at least one of electrostatic discharge protection lines comprises a gap trace part disposed between two adjacent electrostatic discharge protection units. 13 . The display substrate according to claim 12 , wherein an extension direction of the gap trace part is parallel to an inclined direction of at least one of the adjacent two electrostatic discharge protection units. 14

Assignees

Inventors

Classifications

  • wherein the TFTs are in active matrices · CPC title

  • characterised by multiple TFTs · CPC title

  • characterised by the dispositions of the protective arrangements · CPC title

  • H10K59/131Primary

    Interconnections, e.g. wiring lines or terminals · CPC title

  • H10D86/00Primary

    Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates · CPC title

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What does patent US12575277B2 cover?
A display substrate and a display apparatus. The display substrate includes an electrostatic discharge protection circuit, a power supply line, and at least one auxiliary electrode. The electrostatic discharge protection circuit includes multiple electrostatic discharge protection units, at least one of which extends along a first inclined direction, there is a first preset included angle betwe…
Who is the assignee on this patent?
Chengdu Boe Optoelect Tech Co, Boe Technology Group Co Ltd
What technology area does this patent fall under?
Primary CPC classification H10K59/131. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 10 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).