Display substrate and display device

Patent metadata

Field	Value
Publication number	US-12575264-B2
Application number	US-202418995570-A
Country	US
Kind code	B2
Filing date	Apr 1, 2024
Priority date	Apr 1, 2024
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A display substrate includes a base substrate and sub-pixels. The sub-pixel includes a light-emitting element and a driving circuit. The driving circuit includes first to third transistors and a first storage capacitor. The second transistor includes an active portion including a channel portion and first and second electrodes respectively connected to the channel portion on opposite sides of the channel portion. The channel portion includes first and second sub-channel portions and a channel connection portion connected between the first and second sub-channel portions. The display substrate further includes a shielding portion, a layer where the shielding portion is located is on a side of a layer where the active portion of the second transistor is located away from the base substrate. An orthographic projection of the shielding portion on the base substrate at least partially overlaps with an orthographic projection of the channel connection portion on the base substrate.

First claim

What is claimed is:

1 . A display substrate, comprising a display region and a peripheral region around the display region, wherein the display substrate comprises:
a base substrate; and a plurality of sub-pixels on the base substrate, arranged in the display region and in a first direction and/or a second direction, the first direction intersecting with the second direction, wherein the sub-pixel comprises a light-emitting element and a driving circuit electrically connected to the light-emitting element, the driving circuit comprises a plurality of transistors and at least one storage capacitor, the plurality of transistors comprise a first transistor, a second transistor and a third transistor, the at least one storage capacitor comprises a first storage capacitor, a first electrode of the first transistor is configured to receive a data signal, a second electrode of the first transistor is electrically connected to a second electrode plate of the first storage capacitor, a first electrode of the second transistor is electrically connected to a second electrode of the third transistor, and a second electrode of the second transistor is electrically connected to a gate of the third transistor, a first electrode of the third transistor is configured to receive a first power signal, and the gate of the third transistor is electrically connected to a first electrode plate of the first storage capacitor, wherein the second transistor comprises an active portion, the active portion of the second transistor comprises a channel portion, and a first electrode and a second electrode respectively connected to the channel portion on opposite sides of the channel portion, and the channel portion comprises a first sub-channel portion, a second sub-channel portion, and a channel connection portion connected between the first sub-channel portion and the second sub-channel portion; and wherein the display substrate further comprises a shielding portion on the base substrate, a layer in which the shielding portion is located is arranged on a side of a layer in which the active portion of the second transistor is located away from the base substrate, and an orthographic projection of the shielding portion on the base substrate at least partially overlaps with an orthographic projection of the channel connection portion on the base substrate.

2 . The display substrate according to claim 1 , wherein the shielding portion is configured to receive a constant voltage signal.

3 . The display substrate according to claim 2 , wherein the plurality of transistors further comprise a fourth transistor, a first electrode of the fourth transistor is configured to receive a first initialization signal, a second electrode of the fourth transistor is electrically connected to the gate of the third transistor, and the shielding portion is configured to receive the first initialization signal.

4 . The display substrate according to claim 3 , wherein the display substrate further comprises a first initialization signal line configured to transmit the first initialization signal; and
wherein the shielding portion is electrically connected to the first initialization signal line.

5 . The display substrate according to claim 4 , wherein the display substrate comprises a third conductive layer on the base substrate and a second conductive layer on a side of the third conductive layer away from the base substrate, the first initialization signal line is arranged in the second conductive layer;
wherein the second conductive layer further comprises a first initialization connection portion spaced apart from the first initialization signal line, the third conductive layer comprises a second initialization connection portion, the second initialization connection portion is electrically connected to the first initialization signal line and the first initialization connection portion, the first initialization connection portion is further electrically connected to the first electrode of the fourth transistor; and wherein the shielding portion is arranged in the third conductive layer, and the shielding portion and the second initialization connection portion are connected to form an integral structure.

6 . The display substrate according to claim 2 , wherein a second electrode of the light-emitting element is configured to receive a second power signal, and the shielding portion is configured to receive the second power signal.

7 . The display substrate according to claim 6 , wherein the display substrate further comprises a second power signal transmission structure configured to transmit the second power signal, and the shielding portion is electrically connected to the second power signal transmission structure.

8 . The display substrate according to claim 7 , wherein the display substrate comprises a second conductive layer on the base substrate and a first conductive layer on a side of the second conductive layer away from the base substrate;
wherein the second power signal transmission structure comprises a second power signal line arranged in the first conductive layer and a second power grid line arranged in the second conductive layer, the second power grid line extends in the first direction, the second power signal line extends in the second direction, and the second power grid line is electrically connected to the second power signal line; and wherein the shielding portion is arranged in the first conductive layer, and the shielding portion and the second power signal line are connected to form an integral structure.

9 . The display substrate according to claim 2 , wherein the shielding portion is configured to receive the first power signal; or
wherein the plurality of transistors further comprise a fifth transistor, a first electrode of the fifth transistor is configured to receive a reference voltage signal, a second electrode of the fifth transistor is electrically connected to the second electrode of the first transistor, and the shielding portion is configured to receive the reference voltage signal; or wherein the plurality of transistors further comprise an eighth transistor, a first electrode of the eighth transistor is configured to receive a second initialization signal, a second electrode of the eighth transistor is electrically connected to a first electrode of the light-emitting element, and the shielding portion is configured to receive the second initialization signal.

10 . The display substrate according to claim 1 , further comprising a scanning signal line configured to transmit a scanning signal to a gate of the second transistor,
wherein the orthographic projection of the shielding portion on the base substrate is spaced apart from an orthographic projection of the scanning signal line on the base substrate, and/or the orthographic projection of the shielding portion on the base substrate is spaced apart from an orthographic projection of the gate of the second transistor on the base substrate.

11 . The display substrate according to claim 1 , wherein the display substrate comprises an active layer on the base substrate and a light shielding layer between the active layer and the base substrate, a plurality of active portions of the plurality of transistors are arranged in the active layer, and an orthographic projection of the light shielding layer on the base substrate at least partially overlaps with orthographic projections of the plurality of active portions on the base substrate.

12 . The display substrate according to claim 11 , wherein the plurality of transistors further comprise a fourth transistor, a fifth transistor, a sixth transistor, a seventh transisto

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Li Haoyu
• Shi Ling
• Fang Fei
• Ma Hongbo
• Huangfu Lujiang

Classifications

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title