Buried channel transistor structures and processes
US-2023223413-A1 · Jul 13, 2023 · US
US12575210B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-12575210-B2 |
| Application number | US-202318331343-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 8, 2023 |
| Priority date | Jul 8, 2022 |
| Publication date | Mar 10, 2026 |
| Grant date | Mar 10, 2026 |
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An image sensor includes a dual vertical gate including two vertical portions apart from each other by an isolation area in a first direction and vertically extending into a substrate, a connection portion configured to connect the two vertical portions to each other on the two vertical portions, and a device isolation layer on side surfaces of the vertical portions in the first direction, wherein each of the two vertical portions includes an upper vertical portion and a lower vertical portion, a sidewall of the upper vertical portion forms a first inclination angle with a line extending in the first direction, a sidewall of the lower vertical portion forms a second inclination angle with the line extending in the first direction, and the first inclination angle is different from the second inclination angle.
Opening claim text (preview).
What is claimed is: 1 . An image sensor comprising: a dual vertical gate comprising two vertical portions and a connection portion on the two vertical portions, the two vertical portions being spaced apart from each other in a first direction by an isolation area, the two vertical portions extending into a substrate in a second direction, the connection portion connecting the two vertical portions to each other, wherein the second direction is perpendicular to the first direction, wherein the connection portion includes distinct first and second regions, the first region of the connection portion overlapping the two vertical portions of the dual vertical gate, and a bottom surface of the second region of the connection portion being at a higher vertical level than a bottom surface of the first region of the connection portion; and a device isolation layer on side surfaces of the vertical portions, the side surfaces being spaced apart from each other in the first direction, wherein each of the two vertical portions comprises an upper vertical portion and a lower vertical portion, a sidewall of the upper vertical portion forms a first inclination angle with a line extending in the first direction, a sidewall of the lower vertical portion forms a second inclination angle with the line extending in the first direction, and the first inclination angle is different from the second inclination angle. 2 . The image sensor of claim 1 , wherein the isolation area includes silicon and the isolation area extends in a third direction, and the third direction is perpendicular to the first direction and the second direction. 3 . The image sensor of claim 1 , wherein a cross-section of the isolation area perpendicular to the second direction has a rectangular shape. 4 . The image sensor of claim 1 , wherein a cross-section of the isolation area perpendicular to the second direction has a rectangular shape, and a length of the cross-section of the isolation area in a third direction is less than a length of the dual vertical gate in the third direction. 5 . The image sensor of claim 1 , wherein a cross-section of the isolation area perpendicular to the second direction has a trapezoidal shape. 6 . The image sensor of claim 1 , wherein a cross-section of the isolation area perpendicular to the second direction has a T shape. 7 . The image sensor of claim 1 , wherein a top surface of the connection portion is at a higher vertical level than a top surface of the device isolation layer. 8 . An image sensor comprising: a substrate; a dual vertical gate in an upper portion of the substrate; a photoelectric conversion element under the dual vertical gate in the substrate; a device isolation layer adjacent to the dual vertical gate in a first direction, the first direction being parallel to a top surface of the substrate; and a floating diffusion region adjacent to the dual vertical gate in the upper portion of the substrate, wherein the dual vertical gate comprises two vertical portions apart from each other by an isolation area in the first direction, the two vertical portions extending into the substrate in a second direction, wherein the second direction is perpendicular to the first direction, and a connection portion connecting the two vertical portions to each other on the two vertical portions, the connection portion including distinct first and second regions, the first region of the connection portion overlapping the two vertical portions of the dual vertical gate, and a bottom surface of the second region of the connection portion being at a higher vertical level than a bottom surface of the first region of the connection portion, wherein each of the two vertical portions comprises an upper vertical portion and a lower vertical portion, a sidewall of the upper vertical portion forms a first inclination angle with a line extending in the first direction, a sidewall of the lower vertical portion forms a second inclination angle with the line extending in the first direction, and the first inclination angle is different from the second inclination angle. 9 . The image sensor of claim 8 , wherein a top surface of the isolation area is at a same vertical level as a top surface of the device isolation layer. 10 . The image sensor of claim 8 , wherein the isolation area includes silicon and the isolation area extends in a third direction, and the third direction is perpendicular to the first direction and the second direction. 11 . The image sensor of claim 8 , wherein a cross-section of the isolation area perpendicular to the second direction has any one of a rectangular shape, a trapezoidal shape, and a T shape. 12 . The image sensor of claim 11 , wherein a cross-section of the isolation area perpendicular to the second direction has a smaller length in a third direction than a length of the dual vertical gate in the third direction. 13 . The image sensor of claim 8 , wherein a sidewall of the upper vertical portion adjacent to the device isolation layer forms the first inclination angle with the line extending in the first direction, a sidewall of the upper vertical portion adjacent to the isolation area forms a third inclination angle with the line extending in the first direction, and the first inclination angle is different from the third inclination angle. 14 . The image sensor of claim 8 , wherein a sidewall of the lower vertical portion adjacent to the device isolation layer forms the second inclination angle with the line extending in the first direction, a sidewall of the lower vertical portion adjacent to the isolation area forms a fourth inclination angle with the line extending in the first direction, and the second inclination angle is different from the fourth inclination angle. 15 . The image sensor of claim 8 , wherein a bottom surface of the device isolation layer is at a same vertical level as a top surface of the lower vertical portion. 16 . An image sensor comprising: a substrate; a dual vertical gate in an upper portion of the substrate; a gate dielectric layer surrounding at least a portion of the dual vertical gate; a photoelectric conversion element under the gate vertical gate in the substrate; a device isolation layer adjacent to the dual vertical gate in a first direction in the upper portion of the substrate, the first direction being parallel to a top surface of the substrate; and a floating diffusion region adjacent to the dual vertical gate in the upper portion of the substrate, wherein the dual vertical gate comprises two vertical portions apart from each other by an isolation area in the first direction, the two vertical portions vertically extending into the substrate in a second direction, wherein the second direction is perpendicular to the first direction, and a connection portion connecting the two vertical portions to each other on the two vertical portions, wherein the connection portion includes distinct first and second regions, the first region of the connection portion overlapping the two vertical portions of the dual vertical gate, and a bottom surface of the second region of the connection portion being at a higher vertical level than a bottom surface of the first region of the connection portion, wherein each of the two vertical portions comprises an upper vertical portion and a lower vertical portion, a sidewall of the upper vertical portion forms a first inclination angle with a line extending in the first direction, a sidewall of the lower vertical portion forms a second inclination angle with the line extend
characterised by the gate of the transistor · CPC title
Interconnections · CPC title
Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes · CPC title
Pixel isolation structures · CPC title
of CMOS image sensors · CPC title
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