Integrated circuit having transistors with different width source and drain terminals

Patent metadata

Field	Value
Publication number	US-12575174-B2
Application number	US-202318152007-A
Country	US
Kind code	B2
Filing date	Jan 9, 2023
Priority date	Sep 9, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

An integrated circuit includes a first terminal-conductor, a second terminal-conductor, and a gate-conductor between the first terminal-conductor and the second terminal-conductor. The first terminal-conductor intersects both an active-region structure and a power rail. The second terminal-conductor intersects the active-region structure without intersecting the power rail. The gate-conductor intersects the active-region structure and is adjacent to the first terminal-conductor and the second terminal-conductor. A first width of the first terminal-conductor is larger than a second width of the second terminal-conductor by a predetermined amount.

First claim

What is claimed is:

1 . An integrated circuit comprising:
a first power rail and a second power rail extending in a first direction; a first-type active-region structure and a second-type active-region structure extending in the first direction; a first terminal-conductor extending in a second direction perpendicular to the first direction, wherein the first terminal-conductor intersects both the first-type active-region structure and the first power rail; a second terminal-conductor extending in the second direction, wherein the second terminal-conductor intersects the first-type active-region structure without intersecting the first power rail; a first gate-conductor extending in the second direction between the first terminal-conductor and the second terminal-conductor and intersecting the first-type active-region structure, wherein the first gate-conductor is adjacent to the first terminal-conductor and the second terminal-conductor; and wherein a first width of the first terminal-conductor is larger than a second width of the second terminal-conductor by a predetermined amount.

2 . The integrated circuit of claim 1 , further comprising:
a via-connector connecting the first terminal-conductor to the first power rail at an intersection between the first terminal-conductor and the first power rail.

3 . The integrated circuit of claim 1 , further comprising:
a third terminal-conductor extending in the second direction, wherein the third terminal-conductor intersects both the second-type active-region structure and the second power rail; and wherein a third width of the third terminal-conductor is equal to the first width.

4 . The integrated circuit of claim 3 , wherein the third terminal-conductor is aligned with the first terminal-conductor along the second direction.

5 . The integrated circuit of claim 3 , further comprising:
a via-connector connecting the third terminal-conductor to the second power rail at an intersection between the third terminal-conductor and the second power rail.

6 . The integrated circuit of claim 3 , wherein the first gate-conductor further intersects the second-type active-region structure, and the first gate-conductor is adjacent to the third terminal-conductor.

7 . The integrated circuit of claim 3 , further comprising:
a second gate-conductor extending in the second direction and intersecting the second-type active-region structure, wherein the second gate-conductor is adjacent to the third terminal-conductor.

8 . The integrated circuit of claim 1 , further comprising:
a fourth terminal-conductor extending in the second direction, wherein the fourth terminal-conductor intersects the second-type active-region structure without intersecting the second power rail; and wherein a fourth width of the fourth terminal-conductor is equal to the second width.

9 . The integrated circuit of claim 8 , wherein the fourth terminal-conductor is aligned with the second terminal-conductor along the second direction.

10 . The integrated circuit of claim 1 , wherein the first width is larger than the second width by at least 20%.

11 . The integrated circuit of claim 1 , wherein the first width is larger than the second width by at least 10%.

12 . An integrated circuit comprising:
a power rail extending in a first direction; an active-region structure extending in the first direction; two boundary isolation regions in the active-region structure; a plurality of terminal-conductors intersecting the active-region structure between the two boundary isolation regions, wherein each of the terminal-conductors extends in a second direction perpendicular to the first direction, and wherein at least one of the terminal-conductors has a first width and at least one of the terminal-conductors has a second width, and wherein a ratio between the first width and the second width is larger than or equal to a predetermined ratio; a plurality of gate-conductors extending in the second direction; and a plurality of via-connectors, wherein at least one terminal-conductor that is conductively connected to the power rail through one of the via-connectors has the first width.

13 . The integrated circuit of claim 12 , where at least one of the gate-conductors is adjacent to a first terminal-conductor having the first width and a second terminal-conductor having the second width.

14 . The integrated circuit of claim 12 , wherein the two boundary isolation regions are at vertical boundaries of a circuit cell.

15 . The integrated circuit of claim 12 , wherein the ratio between the first width and the second width is at least 1.20.

16 . The integrated circuit of claim 12 , wherein the ratio between the first width and the second width is at least 1.10.

17 . An integrated circuit comprising:
a first power rail extending in a first direction; a first-type active-region structure extending in the first direction; a first terminal-conductor extending in a second direction perpendicular to the first direction, wherein the first terminal-conductor intersects both the first-type active-region structure and the first power rail; a second terminal-conductor extending in the second direction, wherein the second terminal-conductor intersects the first-type active-region structure without intersecting the first power rail; a first gate-conductor extending in the second direction between the first terminal-conductor and the second terminal-conductor and intersecting the first-type active-region structure, wherein the first gate-conductor is adjacent to the first terminal-conductor and the second terminal-conductor; and wherein a first width of the first terminal-conductor is larger than a second width of the second terminal-conductor by a predetermined amount.

18 . The integrated circuit of claim 17 , further comprising:
a via-connector connecting the first terminal-conductor to the first power rail at an intersection between the first terminal-conductor and the first power rail.

19 . The integrated circuit of claim 17 , further comprising:
a second gate-conductor extending in the second direction and intersecting the first-type active-region structure, wherein the first terminal-conductor is adjacent to the first gate-conductor and adjacent to the second gate-conductor.

20 . The integrated circuit of claim 17 , further comprising:
a second gate-conductor extending in the second direction and intersecting the first-type active-region structure, wherein the second terminal-conductor is adjacent to the first gate-conductor and adjacent to the second gate-conductor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Tsmc Nanjing Company Ltd
• Tsmc China Company Ltd

Inventors

• Wang Xinyong
• Chen Cun Cun
• Huang Ying
• Chen Chih-Liang
• Tien Li-Chun

Classifications

• H10W20/427

  Power or ground buses · CPC title

• H10W20/42 Primary

  Vias, e.g. via plugs · CPC title

• H10D84/0186

  Manufacturing their interconnections or electrodes, e.g. source or drain electrodes · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title

• H10D84/85 Primary

  Complementary IGFETs, e.g. CMOS · CPC title