High voltage semiconductor device and method of manufacturing same

Patent metadata

Field	Value
Publication number	US-12575159-B2
Application number	US-202318332795-A
Country	US
Kind code	B2
Filing date	Jun 12, 2023
Priority date	Mar 30, 2023
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

Disclosed are a high voltage semiconductor device and a method of manufacturing the same. More particularly, a high voltage semiconductor device and a method of manufacturing the same include a metal field plate, which may be manufactured substantially simultaneously with a thin film resistor (TFR) (e.g., in the same process step[s] or sequence), between a source metal and a gate electrode.

First claim

What is claimed is:

1 . A high voltage semiconductor device comprising:
a substrate; a drift region in the substrate; a body region in the substrate; a drain in the drift region; a source in the body region; a gate electrode on the substrate; a first insulating layer on the substrate and covering the gate electrode; a source contact in the first insulating layer and connected to the source; a drain contact in the first insulating layer and connected to the drain; a metal field plate in the first insulating layer and electrically connected to the source contact, wherein the metal field plate overlaps an edge of the gate electrode adjacent to the drain; a first wiring layer on the first insulating layer, wherein the first wiring layer includes a source electrode connected to the source contact and a drain electrode connected to the drain contact, and the metal field plate is electrically connected to the source contact through the source electrode; and a thin film resistor in the first insulating layer and spaced apart from the metal field plate, wherein the thin film resistor has a substantially identical chemical composition and thickness as the metal field plate and is substantially at a same height as the metal field plate.

2 . The high voltage semiconductor device of claim 1 , further comprising
a drain extension in the drift region, wherein the drain is in the drain extension.

3 . The high voltage semiconductor device of claim 1 , wherein the metal field plate is thinner than the source electrode.

4 . The high voltage semiconductor device of claim 1 , wherein the metal field plate is spaced apart from an upper surface of the gate electrode.

5 . The high voltage semiconductor device of claim 1 , further comprising:
a second insulating layer on the first wiring layer and the first insulating layer; and a second wiring layer on the second insulating layer.

6 . The high voltage semiconductor device of claim 5 , further comprising
a body contact in the body region and in contact with the source.

7 . The high voltage semiconductor device of claim 1 , further comprising a first via or contact in the first insulating layer connecting the thin film resistor to the first wiring layer.

8 . The high voltage semiconductor device of claim 7 , further comprising a field plate contact in the first insulating layer connecting the metal field plate to the source electrode.

9 . The high voltage semiconductor device of claim 1 , further comprising a field plate contact in the first insulating layer connecting the metal field plate to the source electrode.

10 . The high voltage semiconductor device of claim 1 , wherein each of the metal field plate and the thin film resistor has a thickness from 30 Å to 1000 Å.

11 . The high voltage semiconductor device of claim 1 , wherein each of the metal field plate and the thin film resistor comprises a conductive layer.

12 . The high voltage semiconductor device of claim 11 , wherein the conductive layer comprises a Ni—Cr alloy, a Cr—Si alloy, tantalum nitride (TaN), a conductive chromium-silicon nitride (CrSiN), a conductive chromium-silicon oxide (CrSiO), or titanium nitride (TiN).

13 . A method of manufacturing a high voltage semiconductor device, the method comprising:
forming a drift region and a body region on a substrate; forming a device isolation layer in the substrate; forming a gate insulating layer and a gate electrode on the substrate; forming a drain in the drift region and a source in the body region; forming a lower insulating layer on the substrate to cover the gate electrode; forming a metal field plate and a thin film resistor spaced apart from the metal field plate on the lower insulating layer, wherein the metal field plate overlaps an edge of the gate electrode adjacent to the drain, and the thin film resistor has a substantially identical chemical composition and thickness as the metal field plate; forming an upper insulating layer on the lower insulating layer to cover the metal field plate and the thin film resistor; forming (i) a source contact and a drain contact in the upper and lower insulating layers and (ii) a first via or contact and a field plate contact spaced apart from the source contact and the drain contact in the upper insulating layer, the field plate contact contacting the metal field plate; and forming a source metal, a drain metal, and a first wiring layer spaced apart from each other on the upper insulating layer, the source metal contacting the field plate contact and the source contact, and the drain metal contacting the drain contact.

14 . The method of claim 13 , wherein each of the metal field plate and the thin film resistor has a thickness from 30 Å to 1000 Å.

15 . The method of claim 13 , wherein each of the metal field plate and the thin film resistor comprises a conductive layer.

16 . The method of claim 15 , wherein the conductive layer comprises a Ni—Cr alloy, a Cr—Si alloy, tantalum nitride (TaN), a conductive chromium-silicon nitride (CrSiN), a conductive chromium-silicon oxide (CrSiO), or titanium nitride (TiN).

17 . The method of claim 13 , further comprising forming a drain extension in the drift region, wherein the drain is in the drain extension.

18 . The method of claim 13 , wherein the metal field plate is thinner than the source electrode.

19 . The method of claim 13 , further comprising:
forming a second insulating layer on the first wiring layer and the first insulating layer; and forming a second wiring layer on the second insulating layer.

Assignees

• Db Hitek Co Ltd

Inventors

• Lee Jong Ho

Classifications

• H10D30/603

  having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS] · CPC title

• H10D62/102 Primary

  Constructional design considerations for preventing surface leakage or controlling electric field concentration · CPC title

• H10D30/0281

  of lateral DMOS [LDMOS] FETs · CPC title

• H10D30/65 Primary

  Lateral DMOS [LDMOS] FETs · CPC title

• H10D1/47

  Resistors having no potential barriers · CPC title