Localized anneal of ferroelectric dielectric

Patent metadata

Field	Value
Publication number	US-12575110-B2
Application number	US-202217822215-A
Country	US
Kind code	B2
Filing date	Aug 25, 2022
Priority date	Aug 25, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A semiconductor device includes a ferroelectric random-access memory (FeRAM) cell. The FeRAM includes a ferroelectric dielectric that is annealed to attain its ferroelectric phase by an induced current flow and heating process. The current flow may be induced though a temporary wire that causes heating of the FeRAM cell. The resulting heating or anneal of the ferroelectric dielectric may crystalize the ferroelectric dielectric to embody or result in having ferroelectric properties. The induced current flow and heating process is substantially local to the FeRAM cell, and to ferroelectric dielectric therein, as opposed to a global heating or annealing process in which the entire semiconductor device, or a relatively larger region of semiconductor device, is heated to the requisite annealing temperature of ferroelectric dielectric.

First claim

What is claimed is:

1 . A semiconductor device fabrication method comprising:
forming a ferroelectric random-access memory (FeRAM) cell that includes a ferroelectric dielectric between a top electrode and a bottom electrode; forming a cell vertical interconnect access (VIA) upon the FeRAM cell; forming a temporary wire upon the cell VIA; and annealing the ferroelectric dielectric to attain a ferroelectric phase by inducing current flow though the temporary wire.

2 . The semiconductor device fabrication method of claim 1 , further comprising:
after annealing the ferroelectric dielectric, removing the temporary wire.

3 . The semiconductor device fabrication method of claim 2 , wherein removing the temporary wire comprises mechanically grinding away the temporary wire and retaining at least a portion of the cell VIA.

4 . The semiconductor device fabrication method of claim 1 , wherein annealing the ferroelectric dielectric comprises crystalizing the ferroelectric dielectric to attain a ferroelectric phase.

5 . The semiconductor device fabrication method of claim 4 , wherein the ferroelectric dielectric attains the ferroelectric phase when electric polarization of the ferroelectric dielectric is reversable by application of an electric field to the ferroelectric dielectric.

6 . The semiconductor device fabrication method of claim 1 , wherein the ferroelectric dielectric is formed from Hafnium Oxide.

7 . The semiconductor device fabrication method of claim 1 , wherein the cell VIA and the temporary wire are simultaneously formed by dual damascene processes.

8 . The semiconductor device fabrication method of claim 1 , wherein inducing current flow though the temporary wire comprises:
inducing current flow from the temporary wire though the cell VIA and into the FeRAM cell.

9 . The semiconductor device fabrication method of claim 1 , wherein inducing current flow though the temporary wire comprises electron charging the temporary wire.

10 . A semiconductor device fabrication method comprising:
forming a bottom wire over a substrate; forming a bottom heater contact upon the bottom wire; forming a ferroelectric random-access memory (FeRAM) cell upon the bottom heater contact, the FeRAM cell comprising a ferroelectric dielectric between a top electrode and a bottom electrode; forming a cell vertical interconnect access (VIA) upon the FeRAM cell; forming a temporary wire upon the cell VIA; and annealing the ferroelectric dielectric to attain a ferroelectric phase by inducing current flow though the temporary wire.

11 . The semiconductor device fabrication method of claim 10 , further comprising:
after annealing the ferroelectric dielectric, removing the temporary wire.

12 . The semiconductor device fabrication method of claim 11 , wherein removing the temporary wire comprises mechanically grinding away the temporary wire and retaining at least a portion of the cell VIA.

13 . The semiconductor device fabrication method of claim 10 , wherein annealing the ferroelectric dielectric comprises crystalizing the ferroelectric dielectric to attain a ferroelectric phase.

14 . The semiconductor device fabrication method of claim 13 , wherein the ferroelectric dielectric attains the ferroelectric phase when electric polarization of the ferroelectric dielectric is reversable by application of an electric field to the ferroelectric dielectric.

15 . The semiconductor device fabrication method of claim 10 , wherein the ferroelectric dielectric is formed from Hafnium Oxide.

16 . The semiconductor device fabrication method of claim 10 , wherein the cell VIA and the temporary wire are simultaneously formed by dual damascene processes.

17 . The semiconductor device fabrication method of claim 10 , wherein inducing current flow though the temporary wire comprises:
inducing current flow from the temporary wire though the cell VIA and into the FeRAM cell.

18 . The semiconductor device fabrication method of claim 10 , wherein inducing current flow though the temporary wire comprises electron charging the temporary wire.

19 . The semiconductor device fabrication method of claim 10 , wherein the FeRAM cell further comprises a resistor upon the top electrode.

20 . A method comprising:
forming a ferroelectric random-access memory (FeRAM) cell comprising a ferroelectric layer; forming a temporary conductive structure in electrical contact with the FeRAM cell; and annealing the ferroelectric layer by inducing current flow through the temporary conductive structure to attain a ferroelectric phase transition within the ferroelectric layer.

21 . The method of claim 20 , further comprising:
removing the temporary conductive structure after annealing the ferroelectric layer.

22 . The method of claim 20 , wherein annealing the ferroelectric layer comprises crystallizing the ferroelectric layer.

Assignees

• IBM

Inventors

• Gong Nanbo
• Ando Takashi
• Cohen Guy M
• Miyazoe Hiroyuki

Classifications

• H10B53/30 Primary

  characterised by the memory core region · CPC title

• H10D1/682 Primary

  having dielectrics comprising perovskite structures · CPC title