Method for accelerating generation of VXLAN packet with hardware, method for accelerating removal of VXLAN header with hardware, and method for accelerating modification to VXLAN packet with hardware

US12574265B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12574265-B2
Application numberUS-202318387484-A
CountryUS
Kind codeB2
Filing dateNov 7, 2023
Priority dateNov 11, 2022
Publication dateMar 10, 2026
Grant dateMar 10, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for accelerating the generation of Virtual Extensible Local Area Network (VXLAN) packets with an application specific integrated circuit (ASIC) includes the following steps: determining whether an original packet is an upstream packet; when the original packet is the upstream packet, determining whether the original packet is for a VXLAN egress interface; when the original packet is for the VXLAN egress interface, adding a prototype outer header to the front of the original packet and thereby generating a VXLAN packet; and after generating the VXLAN packet, determining whether to modify the content of the prototype outer header.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method for accelerating generation of Virtual Extensible Local Area Network (VXLAN) packets with hardware, the method comprising: determining whether an original packet is an upstream packet; when the original packet is the upstream packet, determining whether the original packet is for a VXLAN egress interface; when the original packet is for the VXLAN egress interface, adding a prototype outer header to a front of the original packet and thereby generating a VXLAN packet; and after generating the VXLAN packet, determining whether to modify content of the prototype outer header of the VXLAN packet, wherein the prototype outer header includes K field(s) and includes M fields, and the M is an integer greater than one, in which the K is a positive integer greater than one and smaller than the M; the K fields include a Point-to-Point Protocol over Ethernet (PPPoE) field, an Internet Protocol version 4 (IPv4) field or an Internet Protocol version 6 (IPv6) field, and a User Datagram Protocol (UDP) field; the method includes a decision step to determine whether to modify content of the K field(s); and the decision step includes: determining whether a PPPoE length offset of the PPPoE field is zero, and updating content of the PPPoE field when the PPPoE length offset is not zero; determining whether an IPv4/IPv6offset of the IPv4/IPv6 field is zero, and updating content of the IPv4/IPv6 field when the IPv4/IPv6 offset is not zero; determining whether a UDP length offset of the UDP field is zero, and updating content of the UDP field when the UDP length offset is not zero; and determining whether a UDP sport (UDP source port) offset of the UDP field is zero, and updating content of the UDP field when the UDP sport offset is not zero. 2 . The method of claim 1 , further comprising: when the prototype outer header is not stored in a content buffer of a content table of the hardware, acquiring at least a part of the content of the prototype outer header from an upper circuit and storing the prototype outer header in the content buffer. 3 . The method of claim 2 , wherein the content buffer is devoted to the VXLAN egress interface. 4 . The method of claim 2 , wherein the upper circuit executes software and/or firmware to generate the at least a part of the content of the prototype outer header. 5 . The method of claim 4 , wherein the hardware is an Application Specific Integrated Circuit (ASIC), the upper circuit includes a central processing unit (CPU), and both the hardware and the upper circuit are included in a network switch or a network router. 6 . The method of claim 2 , wherein the step of determining whether to modify the content of the prototype outer header of the VXLAN packet includes: acquiring multiple field values from the upper circuit, and storing the multiple field values in multiple fields of a control entry of a control table respectively; and determining whether to modify the content of the prototype outer header of the VXLAN packet according to the control entry. 7 . The method of claim 6 , wherein the control entry is devoted to the VXLAN egress interface. 8 . The method of claim 6 , wherein the upper circuit executes software and/or firmware to generate the multiple field values. 9 . The method of claim 6 , the step of determining whether to modify the content of the prototype outer header of the VXLAN packet according to the control entry includes: checking the content of the K field(s) of the prototype outer header according to the multiple field values of the multiple fields of the control entry and thereby determining whether to modify the content of the K field(s), wherein the K is a positive integer smaller than the M. 10 . The method of claim 1 , further comprising: when the prototype outer header is stored in a content buffer of a content table of the hardware, acquiring the prototype outer header from the content buffer. 11 . The method of claim 10 , wherein the step of determining whether to modify the content of the prototype outer header of the VXLAN packet includes: determining whether to modify the content of the prototype outer header of the VXLAN packet according to a control entry of a control table of the hardware, wherein the control entry includes multiple field values. 12 . The method of claim 11 , wherein the prototype outer header includes M fields, and the M is an integer greater than one; and the step of determining whether to modify the content of the prototype outer header of the VXLAN packet according to the control entry of the control table includes: checking the content of the K field(s) of the prototype outer header according to the multiple field values and thereby determining whether to modify the content of the K field(s), wherein the K is a positive integer smaller than the M.

Assignees

Inventors

Classifications

  • Current supply arrangements · CPC title

  • H04L45/74Primary

    Address processing for routing · CPC title

  • Virtual LANs, VLANs, e.g. virtual private networks [VPN] (LAN interconnection over a bridge based backbone H04L12/462; encapsulation techniques H04L12/4633; routing of packets H04L45/00; packet switches H04L49/00; virtual private networks for security H04L63/0272) · CPC title

  • characterized by the protocol used · CPC title

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What does patent US12574265B2 cover?
A method for accelerating the generation of Virtual Extensible Local Area Network (VXLAN) packets with an application specific integrated circuit (ASIC) includes the following steps: determining whether an original packet is an upstream packet; when the original packet is the upstream packet, determining whether the original packet is for a VXLAN egress interface; when the original packet is fo…
Who is the assignee on this patent?
Realtek Semiconductor Corp
What technology area does this patent fall under?
Primary CPC classification H04L45/74. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 10 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).