Finite impulse response input digital-to-analog converter

Patent metadata

Field	Value
Publication number	US-12574045-B2
Application number	US-202418654911-A
Country	US
Kind code	B2
Filing date	May 3, 2024
Priority date	Nov 3, 2021
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A digital-to-analog converter (DAC) may include an integrator, an input network, and control circuitry. The input network may include a plurality of parallel taps, each having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member is coupled between an input of the digital-to-analog converter and an input of the integrator. The control circuitry may be configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the DAC, such that the control circuitry enables, substantially contemporaneously, an even number of members at a time in order to increase the analog gain, with half of such enabled members in a first group and half of such enabled members in a second group.

First claim

What is claimed is:

1 . A digital-to-analog converter, comprising:
an integrator; an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member of the plurality of parallel taps is coupled between an input of the digital-to-analog converter and an input of the integrator; and control circuitry configured to selectively enable and disable particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter, such that the control circuitry enables, substantially contemporaneously, an even number of members at a time in order to increase the analog gain, with half of such enabled members in a first group and half of such enabled members in a second group.

2 . The digital-to-analog converter of claim 1 , wherein the first group and the second group are separated temporally from each other in terms of their respective signal delays in order to facilitate matching of an input signal received by the digital-to-analog converter and an output of a component downstream of the digital-to-analog converter.

3 . The digital-to-analog converter of claim 1 , wherein the control circuitry is further configured to, when enabling or disabling additional members of the plurality of parallel taps to modify an analog gain, alternate between tap delays that decrease a duration between a first center of the first group and a second center of the second group and tap delays that increase the duration.

4 . The digital-to-analog converter of claim 3 , wherein the control circuitry is further configured to maintain the first center at approximately 25% of a pulse width of an input signal received by the digital-to-analog converter and at approximately 75% of a pulse width of the input signal.

5 . A method comprising, in a digital-to-analog converter having an integrator and an input network comprising a plurality of parallel taps, each member of the plurality of parallel taps having a signal delay such that at least two of the signal delays of the members of the plurality of parallel taps are different, and wherein each member of the plurality of parallel taps is coupled between an input of the digital-to-analog converter and an input of the integrator:
selectively enabling and disabling, substantially contemporaneously, particular members of the plurality of parallel taps in order to program an effective input resistance of the input network to control an analog gain of the digital-to-analog converter, such an even number of members are enabled at a time in order to increase the analog gain, with half of such enabled members in a first group and half of such enabled members in a second group.

6 . The method of claim 5 , wherein the first group and the second group are separated temporally from each other in terms of their respective signal delays in order to facilitate matching of an input signal received by the digital-to-analog converter and an output of a component downstream of the digital-to-analog converter.

7 . The method of claim 5 , further comprising to, when enabling or disabling additional members of the plurality of parallel taps to modify an analog gain, alternating between tap delays that decrease a duration between a first center of the first group and a second center of the second group and tap delays that increase the duration.

8 . The method of claim 7 , further comprising maintaining the first center at approximately 25% of a pulse width of an input signal received by the digital-to-analog converter and at approximately 75% of a pulse width of the input signal.

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Melanson John L
• Zhang Lingli
• Astrachan Paul M
• Kelton James

Classifications

• H03M1/1023

  Offset correction (H03M1/1019 takes precedence; removal of offset already present on the analogue input signal H03M1/1295) · CPC title

• H03M1/06

  Continuously compensating for, or preventing, undesired influence of physical parameters (periodically, {e.g. by using stored correction values,} H03M1/10) · CPC title

• H03M1/183

  the feedback signal controlling the gain of an amplifier or attenuator preceding the analogue/digital converter · CPC title

• H03G3/001

  Digital control of analog signals · CPC title

• H03M1/822 Primary

  using pulse width modulation · CPC title