Power efficient array discharge for program boosting

Patent metadata

Field	Value
Publication number	US-12573454-B2
Application number	US-202217732117-A
Country	US
Kind code	B2
Filing date	Apr 28, 2022
Priority date	Apr 28, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

Systems, apparatuses and methods may provide for technology that issues a program pulse to a selected subblock of a NAND memory array, conducts a pulse recovery phase after the program pulse, and shuts down unselected subblocks in the NAND memory array during the pulse recovery phase.

First claim

We claim:

1 . A memory chip controller comprising:
one or more substrates; and logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to:
issue a program pulse to a selected subblock of a NAND memory array;
conduct a pulse recovery phase after the program pulse, including during the pulse recovery phase, applying an inhibit voltage to a selected word line coupled to the selected subblock, and controlling the selected word line to drop from the inhibit voltage to a pass voltage that is above a ground level; and
shut down unselected subblocks in the NAND memory array during the pulse recovery phase.

2 . The memory chip controller of claim 1 , wherein the unselected subblocks include a first set of unselected subblocks that share a source-side select gate with the selected subblock and a second set of unselected subblocks that do not share the source-side select gate with the selected subblock.

3 . The memory chip controller of claim 2 , wherein the logic is further to:
apply a verify voltage to the selected word line in the NAND memory array; conduct a verify recovery phase after application of the verify voltage to the selected word line; shut down one or more subblocks in the first set of unselected subblocks during the verify recovery phase; and shut down one or more subblocks in the second set of unselected subblocks during the verify recovery phase.

4 . The memory chip controller of claim 3 , wherein the logic is further to turn on the one or more subblocks in the first set of unselected subblocks based on a loop type associated with the program pulse.

5 . The memory chip controller of claim 1 , wherein to conduct the pulse recovery phase, the logic is to:
apply the inhibit voltage to one or more unselected word lines in the NAND memory array; and apply the pass voltage to a set of word lines and select gates in the NAND memory array, wherein the unselected subblocks are shut down while the pass volage is applied.

6 . The memory chip controller of claim 1 , wherein the selected subblock is to be located at an intersection of a drain-side select gate and a word line.

7 . The memory chip controller of claim 1 , wherein the logic is to adjust a bias of the unselected subblocks based on a leakage constraint.

8 . The memory chip controller of claim 1 , wherein the program pulse corresponds to a program voltage that is higher than the inhibit voltage, and the program voltage, the inhibit voltage, and the pass voltage are three successively dropping voltage steps applied on the selected word line.

9 . The memory chip controller of claim 1 , wherein while the program pulse is applied on the selected word line, the inhibit voltage is applied to an unselected word line and extended to the pulse recovery phase.

10 . A computing system comprising:
a NAND memory array; and a memory chip controller coupled to the NAND memory array, wherein the memory chip controller includes logic implemented at least partly in one or more of configurable or fixed-functionality hardware, the logic to:
issue a program pulse to selected subblock of the NAND memory array;
conduct a pulse recovery phase after the program pulse, including during the pulse recovery phase, applying an inhibit voltage to a selected word line coupled to the selected subblock, and controlling the selected word line to drop from the inhibit voltage to a pass voltage that is above a ground level; and
shut down unselected subblocks in the NAND memory array during the pulse recovery phase.

11 . The computing system of claim 10 , wherein the unselected subblocks include a first set of unselected subblocks that share a source-side select gate with the selected subblock and a second set of unselected subblocks that do not share the source-side select gate with the selected subblock.

12 . The computing system of claim 11 , wherein the logic is further to:
apply a verify voltage to the selected word line in the NAND memory array; conduct a verify recovery phase after application of the verify voltage to the selected word line; shut down one or more subblocks in the first set of unselected subblocks during the verify recovery phase; and shut down one or more subblocks in the second set of unselected subblocks during the verify recovery phase.

13 . The computing system of claim 12 , wherein the logic is further to turn on the one or more subblocks in the first set of unselected subblocks based on a loop type associated with the program pulse.

14 . The computing system of claim 10 , wherein to conduct the pulse recovery phase, the logic is to:
apply the inhibit voltage to one or more unselected word lines in the NAND memory array and apply the pass voltage to a set of word lines and select gates in the NAND memory array, wherein the unselected subblocks are shut down while the pass volage is applied.

15 . The computing system of claim 10 , wherein the selected subblock is to be located at an intersection of a drain-side select gate and a word line.

16 . The computing system of claim 10 , wherein the logic is to adjust a bias of the unselected subblocks based on a leakage constraint.

17 . A method comprising:
issuing a program pulse to a selected subblock of a NAND memory array; conducting a pulse recovery phase after the program pulse, including during the pulse recovery phase, applying an inhibit voltage to a selected word line coupled to the selected subblock, and controlling the selected word line to drop from the inhibit voltage to a pass voltage that is above a ground level; and shutting down unselected subblocks in the NAND memory array during the pulse recovery phase.

18 . The method of claim 17 , wherein the unselected subblocks include a first set of unselected subblocks that share a source-side select gate with the selected subblock and a second set of unselected subblocks that do not share the source-side select gate with the selected subblock.

19 . The method of claim 18 , further including:
applying a verify voltage to the selected word line in the NAND memory array; conducting a verify recovery phase after application of the verify voltage to the selected word line; shutting down one or more subblocks in the first set of unselected subblocks during the verify recovery phase; and shutting down one or more subblocks in the second set of unselected subblocks during the verify recovery phase.

20 . The method of claim 19 , further including turning on the one or more subblocks in the first set of unselected subblocks based on a loop type associated with the program pulse.

Assignees

• Intel NDTM US LLC

Inventors

• Ameen Tarek
• Rajwade Shantanu
• Chang Hsiao Yu
• Shenoy Rohit
• Chava Pranav
• Sun Xin
• Chandrapati Pratyush

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/32

  Timing circuits · CPC title

• G11C16/30

  Power supply circuits · CPC title