Pixel circuit and driving method thereof, and display panel

Patent metadata

Field	Value
Publication number	US-12573341-B2
Application number	US-202218270094-A
Country	US
Kind code	B2
Filing date	Jul 15, 2022
Priority date	Jul 30, 2021
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A pixel circuit and a driving method thereof, and a display panel. The pixel circuit includes a driving circuit, a data writing circuit, a compensation control circuit, an energy storage circuit, a first light-emitting control circuit, a second light-emitting control circuit, a first initialization circuit, a second initialization circuit, and a transmission circuit. The driving circuit includes a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the first terminal and the second terminal and used for driving a light-emitting element to emit light. The first initialization circuit is configured to apply a first initialization voltage to the control terminal of the driving circuit; the second initialization circuit is configured to apply a second initialization voltage to the first electrode of the light-emitting element.

First claim

The invention claimed is:

1 . A pixel circuit, comprising: a driving circuit, a data writing circuit, a compensation control circuit, an energy storage circuit, a first light emission control circuit, a second light emission control circuit, a first initialization circuit, a second initialization circuit and a transmission circuit; wherein the driving circuit comprises a control terminal, a first terminal and a second terminal, and is configured to control a driving current flowing through the first terminal and the second terminal for driving a light-emitting element to emit light; the data writing circuit is configured to write a data signal into the first terminal of the driving circuit under a control of a first scanning signal; the compensation control circuit is configured to compensate for the driving circuit under a control of a second scanning signal; the energy storage circuit is configured to store a voltage of the control terminal of the driving circuit; the first light emission control circuit is configured to apply a first power supply voltage of a first power supply terminal to the first terminal of the driving circuit under a control of a first light emission control signal; the second light emission control circuit is configured to apply the driving current to a first electrode of the light-emitting element under a control of a second light emission control signal; the first initialization circuit is configured to apply a first initialization voltage to the control terminal of the driving circuit under a control of a first reset control signal; the transmission circuit is configured to transmit the first initialization voltage under a control of a transmission control signal; and the second initialization circuit is configured to apply a second initialization voltage to the first electrode of the light-emitting element under a control of a second reset control signal, wherein the first initialization circuit and the transmission circuit are jointly configured to apply the first initialization voltage to the control terminal of the driving circuit, and the compensation control circuit is further configured to transmit the first initialization voltage of the control terminal of the driving circuit to the second terminal of the driving circuit under a control of the second scanning signal, wherein the second initialization circuit comprises a seventh transistor, the seventh transistor is an N-type oxide thin film transistor, the second reset control signal and the first light emission control signal or the second light emission control signal are a same control signal; and the transmission control signal and the second light emission control signal or the first light emission control signal are a same control signal, the first initialization circuit comprises a first transistor, and the transmission circuit comprises an eighth transistor, the first transistor and the eighth transistor are P-type thin film transistors, and a value of a width-length ratio of a channel region of the first transistor is in a range of [1/3, 3/4], and a value of a width-length ratio of a channel region of the eighth transistor is in a range of [1/3, 3/4].

2 . The pixel circuit according to claim 1 , wherein the driving circuit comprises a third transistor;
a gate electrode of the third transistor serves as the control terminal of the driving circuit, a first electrode of the third transistor serves as the first terminal of the driving circuit, and a second electrode of the third transistor serves as the second terminal of the driving circuit.

3 . The pixel circuit according to claim 2 , wherein the data writing circuit comprises a fourth transistor;
a gate electrode of the fourth transistor is connected to a first scanning signal terminal to receive the first scanning signal, a first electrode of the fourth transistor is connected to a data signal terminal to receive the data signal, and a second electrode of the fourth transistor is connected to the first terminal of the driving circuit.

4 . The pixel circuit according to claim 3 , wherein the compensation control circuit comprises a second transistor, and the energy storage circuit comprises a storage capacitor;
a gate electrode of the second transistor is connected to a second scanning signal terminal to receive the second scanning signal, a first electrode of the second transistor is connected to the second terminal of the driving circuit, and a second electrode of the second transistor is connected to the control terminal of the driving circuit, a first electrode of the storage capacitor is coupled with the control terminal of the driving circuit, and a second electrode of the storage capacitor is coupled with the first power supply terminal.

5 . The pixel circuit according to claim 4 , wherein the second transistor is an N-type oxide thin film transistor, and the N-type oxide thin film transistor comprises a first metal layer, an active layer and a second metal layer which are sequentially stacked and insulated from each other,
in an extension direction of the active layer, a width of the second metal layer is not greater than a width of the first metal layer; the second metal layer and the second scanning signal terminal are connected so as to serve as the gate electrode of the second transistor, or, both of the second metal layer and the first metal layer are connected to the second scanning signal terminal to serve as the gate electrode of the second transistor at the same time; the active layer comprises a channel region covered by the first metal layer, and a value of a width-length ratio of the channel region of the N-type oxide thin film transistor is in a range of [1/2, 7/8].

6 . The pixel circuit according to claim 4 , wherein the first light emission control circuit comprises a fifth transistor,
a gate electrode of the fifth transistor is connected to a first light emission control signal terminal to receive the first light emission control signal, a first electrode of the fifth transistor is connected to the first power supply terminal to receive the first power supply voltage, and a second electrode of the fifth transistor is connected to the first terminal of the driving circuit.

7 . The pixel circuit according to claim 6 , wherein the second light emission control circuit comprises a sixth transistor,
a gate electrode of the sixth transistor is connected to a second light emission control signal terminal to receive the second light emission control signal, a first electrode of the sixth transistor is connected to the second terminal of the driving circuit, and a second electrode of the sixth transistor is connected to the first electrode of the light-emitting element.

8 . The pixel circuit according to claim 7 , wherein
a gate electrode of the seventh transistor is connected to a second reset control signal terminal to receive the second reset control signal, a first electrode of the seventh transistor is connected to a second initialization voltage terminal to receive the second initialization voltage, and a second electrode of the seventh transistor is connected to the first electrode of the light-emitting element.

9 . The pixel circuit according to claim 8 , wherein
a gate electrode of the first transistor is connected to a first reset control signal terminal to receive the first reset control signal, a first electrode of the first transistor is connected to a first initialization voltage terminal to receive the first initialization voltage, and a second electrode of the first transistor is connected to a first electrode of the eighth transistor; a gate electrode of the eighth transistor is connected to a transmission control signal terminal to receive the tr

Assignees

• Chengdu Boe Optoelect Tech Co
• Boe Technology Group Co Ltd

Inventors

• Liu Cong
• Wang Benlian
• Huang Yao
• Huang Weiyun
• Wang Binyan

Classifications

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2300/0452

  Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

• H10K59/1216

  the pixel elements being capacitors · CPC title

• H10K59/126

  Shielding, e.g. light-blocking means over the TFTs · CPC title

• G09G3/3275

  Details of drivers for data electrodes · CPC title