Driving signal generation circuit, method, module and display device

Patent metadata

Field	Value
Publication number	US-12573340-B2
Application number	US-202218552217-A
Country	US
Kind code	B2
Filing date	Jul 29, 2022
Priority date	Jul 29, 2022
Publication date	Mar 10, 2026
Grant date	Mar 10, 2026

Abstract

A driving signal generation circuit includes a first node generation circuit, a second node generation circuit, a third node generation circuit, a first control node control circuit, a second control node control circuit and an output circuit; the second control node control circuit is configured to control to connect the second control node and the first clock signal terminal under the control of the potential of the second control node, and control the potential of the second control node according to the potential of the second node; the output circuit is configured to output corresponding driving signal through the driving signal output terminal under the control of the potential of the first control node and the potential of the second control node.

First claim

What is claimed is:

1 . A driving signal generation circuit, comprising a first node generation circuit, a second node generation circuit, a third node generation circuit, a first control node control circuit, a second control node control circuit and an output circuit, wherein
the first node generation circuit is electrically connected to a first node, and is configured to control a potential of the first node; the second node generation circuit is electrically connected to a second node, and is configured to control a potential of the second node; the third node generation circuit is electrically connected to the first node and a third node respectively, and is configured to control a potential of the third node according to the potential of the first node; the first control node control circuit is electrically connected to the third node and a first control node respectively, and is configured to control a potential of the first control node according to the potential of the third node; the second control node control circuit is respectively electrically connected to a first clock signal terminal, the second node and a second control node, and is configured to control to connect the second control node and the first clock signal terminal under the control of the potential of the second control node, and control a potential of the second control node according to the potential of the second node; the output circuit is electrically connected to the first control node, the second control node, and the driving signal output terminal, respectively, and is configured to output a corresponding driving signal through the driving signal output terminal under the control of the potential of the first control node and the potential of the second control node; wherein the second node and the second control node are different nodes; wherein the driving signal generation circuit further comprises a first node control circuit and/or a second node control circuit; wherein the first node control circuit is electrically connected to the first control node, the second control node and a first voltage terminal, and is configured to control to connect the first control node and the first voltage terminal under the control of the potential of the second control node; the second node control circuit is electrically connected to the third node, the second control node and a first voltage terminal, and is configured to control to connect the second control node and the first voltage terminal under the control of the potential of the third node.

2 . The driving signal generation circuit according to claim 1 , wherein the first node generation circuit is further connected to the second node, the first clock signal terminal, a second clock signal terminal, an input terminal and the first voltage terminal, is configured to control to connect the first node and the input terminal under the control of a second clock signal provided by the second clock signal terminal, and control to connect the first node and the first voltage terminal under the control of the potential of the second node and a first clock signal provided by the first clock signal terminal;
the second node generation circuit is also electrically connected to the second clock signal terminal, a second voltage terminal and the first node, is configured to control to connect the second node and the second voltage terminal under the control of the second clock signal, is configured to control to connect the second clock signal terminal and the second node under the control of the potential of the first node; the third node generation circuit is also electrically connected to the first clock signal terminal, and is configured to control to connect the third node and the first clock signal terminal under the control of the potential of the first node, and adjust the potential of the third node according to the potential of the first node.

3 . The driving signal generation circuit according to claim 2 , wherein the first node generation circuit comprises a first transistor (T 19 ), a second transistor (T 20 ), and a third transistor (T 21 );
a control electrode of the first transistor (T 19 ) is electrically connected to the second clock signal terminal, a first electrode of the first transistor (T 19 ) is electrically connected to the input terminal, and a second electrode of the first transistor (T 19 ) is electrically connected to the first node; a control electrode of the second transistor (T 20 ) is electrically connected to the first clock signal terminal, a first electrode of the second transistor (T 20 ) is electrically connected to the first node, and a second electrode of the second transistor (T 20 ) is electrically connected to a first electrode of the third transistor (T 21 ), and a second electrode of the third transistor (T 21 ) is electrically connected to the first voltage terminal; the second node generation circuit includes a fourth transistor (T 22 ) and a fifth transistor (T 23 ); a control electrode of the fourth transistor (T 22 ) is electrically connected to the second clock signal terminal, a first electrode of the fourth transistor (T 22 ) is electrically connected to the second voltage terminal, and a second electrode of the twenty-second is electrically connected to the second node; a control electrode of the fifth transistor (T 23 ) is electrically connected to the first node, a first electrode of the fifth transistor (T 23 ) is electrically connected to the second clock signal terminal, and a second electrode of the fifth transistor (T 23 ) is electrically connected to the second node; the third node generation circuit includes a sixth transistor (T 24 ) and a first capacitor (C 2 ); a control electrode of the sixth transistor (T 24 ) is electrically connected to the first node, a first electrode of the sixth transistor (T 24 ) is electrically connected to the first clock signal terminal, and a second electrode of the sixth transistor (T 24 ) is electrically connected to the third node; a first terminal of the first capacitor (C 2 ) is electrically connected to the first node, and a second terminal of the first capacitor (C 2 ) is electrically connected to the third node.

4 . The driving signal generation circuit according to claim 1 , wherein the second control node control circuit comprises a first transistor (T 1 ) and a first capacitor (C 1 );
a control electrode of the first transistor (T 1 ) is electrically connected to the second node, a first electrode of the first transistor (T 1 ) is electrically connected to the first clock signal terminal, and a second electrode of the first transistor (T 1 ) is electrically connected to the second control node; a first terminal of the first capacitor (C 1 ) is electrically connected to the second node, and a second terminal of the first capacitor (C 1 ) is electrically connected to the second control node.

5 . The driving signal generation circuit according to claim 4 , wherein the second control node control circuit further comprises a second transistor (T 11 ); the second electrode of the first transistor (T 1 ) is electrically connected to the second control node through the second transistor (T 11 );
a control electrode of the second transistor (T 11 ) is electrically connected to the first clock signal terminal, a first electrode of the second transistor (T 11 ) is electrically connected to the second control node, and a second electrode of the second transistor (T 11 ) is electrically connected to the second electrode of the first transistor (T 1 ).

6 . The driving signal generation circuit according to claim 1 , wherein the first control node control circuit is further electrically connected to the first clock signal terminal, and is configured to control

Assignees

• Hefei Boe Joint Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Feng Xuehuan
• Xu Pan
• Li Yongqian

Classifications

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title