Display substrate and manufacturing method therefor, and display apparatus

Patent metadata

Field	Value
Publication number	US-12568744-B2
Application number	US-202418938307-A
Country	US
Kind code	B2
Filing date	Nov 6, 2024
Priority date	Sep 28, 2020
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A display substrate and a manufacturing method therefor, and a display apparatus. The display substrate includes a base substrate, a second power line, a data signal line and a plurality of sub-pixels, wherein at least one sub-pixel includes a pixel driving circuit and a light emitting device connected to the pixel driving circuit; a semiconductor layer and a plurality of conducting layers, which are disposed at one side of the semiconductor layer away from the base substrate, are disposed on the base substrate, a first electrode is arranged in at least one conducting layer, the first electrode is connected to the second power line, and there is an overlapping area between an orthographic projection of the first electrode on the base substrate and an orthographic projection of the data signal line on the base substrate.

First claim

The invention claimed is:

1 . A display substrate, comprising a base substrate, a second power line, a data signal line and a plurality of sub-pixels, wherein at least one sub-pixel comprises a pixel driving circuit and a light emitting device connected to the pixel driving circuit, wherein the pixel driving circuit at least comprises a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor;
wherein a first pole of the first transistor is connected to the data signal line, and a second pole of the first transistor is connected to a second node; a first pole of the second transistor is connected to a first node, and a second pole of the second transistor is connected to a third node; a gate electrode of the third transistor is connected to the first node to control a driving current flowing through the third transistor; a first pole of the fourth transistor is connected to an initial signal line; and a first pole of the fifth transistor is connected to a reference signal line, and a second pole of the fifth transistor is connected to the second node; wherein the pixel driving circuit further comprises a threshold capacitor comprising a threshold capacitor first polar plate and a threshold capacitor second polar plate; and the threshold capacitor second polar plate is connected to the second node, and the threshold capacitor first polar plate is connected to the first node; wherein the second pole of the fifth transistor is connected to the threshold capacitor second polar plate via a fourth connection electrode; wherein a semiconductor layer and a plurality of conducting layers, which are arranged at one side of the semiconductor layer away from the base substrate, are arranged on the base substrate, a first electrode is arranged in at least one conducting layer, the first electrode is connected to the second power line, and there is an overlapping area between an orthographic projection of the first electrode on the base substrate and an orthographic projection of the data signal line on the base substrate; wherein the second pole of the first transistor is electrically connected to the threshold capacitor second polar plate through the fourth connection electrode; wherein an orthographic projection of the fourth connection electrode on the base substrate overlaps with an orthographic projection of the second power line on the base substrate.

2 . The display substrate according to claim 1 , wherein
the first electrode comprises a first electrode segment extending along a first direction and a second electrode segment extending along a second direction, there is an overlapping area between an orthographic projection of the second electrode segment on the base substrate and the orthographic projection of the data signal line on the base substrate.

3 . The display substrate according to claim 2 , wherein the second power line at least partially extends along the second direction and the reference signal line at least partially extends along the second direction.

4 . The display substrate according to claim 3 , wherein the orthographic projection of the data signal line on the base substrate is located between an orthographic projection of the reference signal line on the base substrate and an orthographic projection of the second power line on the base substrate.

5 . The display substrate according to claim 2 , wherein the reference signal line at least partially extends along the second direction, and there is an overlapping area between an orthographic projection of the reference signal line on the base substrate and an orthographic projection of the first electrode on the base substrate.

6 . The display substrate according to claim 1 , wherein
the plurality of conducting layers comprise a first conducting layer, a second conducting layer, a third conducting layer and a fourth conducting layer arranged sequentially at one side of the semiconductor layer away from the base substrate, the data signal line is arranged in the fourth conducing layer, and the first electrode is arranged in the first conducting layer, the second conducting layer or the third conducting layer.

7 . The display substrate according to claim 6 , wherein the second power line is arranged in the fourth conducting layer, and the second power line is connected to the first electrode through a via hole.

8 . The display substrate according to claim 6 , wherein
the first electrode is arranged in the first conducting layer or the second conducting layer, an interlayer connecting electrode is also arranged in the third conducting layer, the interlayer connecting electrode is connected to the first electrode through a via hole, and the second power line is connected to the interlayer connecting electrode through a via hole.

9 . The display substrate according to claim 6 , wherein
the fourth transistor is a double-gate transistor, and at least comprises a fourth active layer arranged in the semiconductor layer and two fourth gate electrodes; and the display substrate further comprises a first sub-polar plate, and there is an overlapping area between an orthographic projection of the first sub-polar plate on the base substrate and an orthographic projection of the fourth active layer, located between the two fourth gate electrodes, on the base substrate; wherein the two fourth gate electrodes are arranged in the first conducting layer, the first sub-polar plate is arranged in the second conducting layer.

10 . The display substrate according to claim 6 , wherein
the fifth transistor is a double-gate transistor, and at least comprises a fifth active layer arranged in the semiconductor layer and two fifth gate electrodes; and the display substrate further comprises a second sub-polar plate, and there is an overlapping area between an orthographic projection of the second sub-polar plate on the base substrate and an orthographic projection of the fifth active layer, located between the two fifth gate electrodes, on the base substrate; wherein the two fifth gate electrodes are arranged in the first conducting layer, the second sub-polar plate is arranged in the second conducting layer.

11 . The display substrate according to claim 10 , wherein
the first transistor is a double-gate transistor, and at least comprises a first active layer arranged in the semiconductor layer and two first gate electrodes; and the display substrate further comprises a third sub-polar plate, and there is an overlapping area between an orthographic projection of the third sub-polar plate on the base substrate and an orthographic projection of the first active layer, located between the two first gate electrodes, on the base substrate; wherein the two first gate electrodes are arranged in the first conducting layer, the third sub-polar plate is arranged in the second conducting layer.

12 . The display substrate according to claim 11 , wherein the second sub-polar plate and the third sub-polar plate are electrically connected.

13 . The display substrate according to claim 11 , wherein
the second transistor is a double-gate transistor, and at least comprises a second active layer arranged in the semiconductor layer and two second gate electrodes; and the display substrate further comprises a fourth sub-polar plate, and there is an overlapping area between an orthographic projection of the fourth sub-polar plate on the base substrate and an orthographic projection of the second active layer, located between the two second gate electrodes, on the base substrate; wherein the two second gate electrodes are arranged in the first conducting

Assignees

• Boe Technology Group Co Ltd

Inventors

• Zheng Can
• Wang Li
• Zhang Hao
• Chen Yipeng
• Liu Ke

Classifications

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2310/0278

  Details of driving circuits arranged to drive both scan and data electrodes · CPC title

• G09G2300/0852

  being a dynamic memory with more than one capacitor · CPC title

• G09G3/3291

  in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements · CPC title