Semiconductor device including capacitor and method for fabricating the same

US12568634B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-12568634-B2
Application numberUS-202318300388-A
CountryUS
Kind codeB2
Filing dateApr 14, 2023
Priority dateNov 2, 2022
Publication dateMar 3, 2026
Grant dateMar 3, 2026

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A method for fabricating a semiconductor device includes: forming a first oxide layer containing a first element over a first electrode layer; forming a second oxide layer containing a second element over the first oxide layer; forming a stacked structure in which a plurality of first oxide layers and a plurality of second oxide layers are alternately stacked by repeating the forming of the first oxide layer and the forming of the second oxide layer a plurality of times; and forming a second electrode layer over the stacked structure, wherein a thickness of a lowermost first oxide layer among the plurality of first oxide layers is greater than a thickness of each of other first oxide layers.

First claim

Opening claim text (preview).

What is claimed is: 1 . A method for fabricating a semiconductor device, comprising: forming a first oxide layer including a first element over a first electrode layer; forming a second oxide layer including a second element over the first oxide layer; forming a stacked structure in which a plurality of first oxide layers and a plurality of second oxide layers are alternately stacked by repeating the forming of the first oxide layer and the forming of the second oxide layer a plurality of times; and forming a second electrode layer over the stacked structure, wherein a thickness of a lowermost first oxide layer among the plurality of first oxide layers is greater than a thickness of each of other first oxide layers. 2 . The method according to claim 1 , wherein the forming of the first oxide layer is performed by an Atomic Layer Deposition (ALD) process, and wherein the number of cycles of the ALD process for forming the lowermost first oxide layer is greater than the number of cycles of the ALD process for forming each of the other first oxide layers. 3 . The method according to claim 1 , wherein a thickness of a lowermost second oxide layer among the plurality of second oxide layers is greater than a thickness of each of other second oxide layers. 4 . The method according to claim 3 , wherein the forming of the second oxide layer is performed by an ALD process, and wherein the number of cycles of the ALD process for forming the lowermost second oxide layer is greater than the number of cycles of the ALD process for forming each of the other second oxide layers. 5 . The method according to claim 1 , wherein a thickness of the lowermost first oxide layer is in a range of 90% to 110% of a thickness of a lowermost second oxide layer among the plurality of second oxide layers. 6 . The method according to claim 1 , wherein a thickness of a Nth first oxide layer among the plurality of first oxide layers is in a range of 90% to 110% of a thickness of a Nth second oxide layer among the plurality of second oxide layers. 7 . The method according to claim 1 , wherein thicknesses of the plurality of first oxide layers decrease from bottom to top. 8 . The method according to claim 1 , wherein thicknesses of the plurality of second oxide layers decrease from bottom to top. 9 . The method according to claim 1 , further comprising: performing a heat treatment on the stacked structure to form a dielectric layer including an oxide of the first element and the second element. 10 . The method according to claim 1 , further comprising: performing a heat treatment on the stacked structure, wherein, during the heat treatment, a first reactive oxide layer including an oxide of the first element and the second element is formed by a reaction between an upper portion of the lowermost first oxide layer and a lower portion of a lowermost second oxide layer among the plurality of second oxide layers, wherein a lower portion of the lowermost first oxide layer remains under the first reactive oxide layer, and wherein an upper portion of the lowermost second oxide layer remains over the first reactive oxide layer. 11 . The method according to claim 10 , wherein, during the heat treatment, a second reactive oxide layer including an oxide of the first element and the second element is formed by a reaction between the other first oxide layers and the other second oxide layers. 12 . The method according to claim 1 , further comprising: performing an additional oxidation process for compensating for oxygen vacancies in the first oxide layer after the forming of the first oxide layer; and performing an additional oxidation process for compensating for oxygen vacancies in the second oxide layer after the forming of the second oxide layer. 13 . The method according to claim 1 , wherein the first oxide layer includes hafnium oxide, and wherein the second oxide layer includes zirconium oxide.

Assignees

Inventors

Classifications

  • the material containing zirconium, e.g. ZrO2 · CPC title

  • the material containing hafnium, e.g. HfO2 · CPC title

  • Laminate layers, e.g. stacks of alternating high-k metal oxides (adhesion layers or buffer layers H10P14/6508, H10P14/6548) · CPC title

  • having a storage electrode stacked over the transistor · CPC title

  • the capacitor extending over the transistor · CPC title

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What does patent US12568634B2 cover?
A method for fabricating a semiconductor device includes: forming a first oxide layer containing a first element over a first electrode layer; forming a second oxide layer containing a second element over the first oxide layer; forming a stacked structure in which a plurality of first oxide layers and a plurality of second oxide layers are alternately stacked by repeating the forming of the fir…
Who is the assignee on this patent?
Sk Hynix Inc
What technology area does this patent fall under?
Primary CPC classification H10D1/696. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Mar 03 2026 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).