Low-power optical input/output chiplet for ethernet switches (TeraPHYe)

Patent metadata

Field	Value
Publication number	US-12567920-B2
Application number	US-202117527483-A
Country	US
Kind code	B2
Filing date	Nov 16, 2021
Priority date	Nov 20, 2020
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A network switch system-in-package includes a carrier substrate with a network switch chip and a plurality of photonic input/output modules disposed on the carrier substrate. Each of the plurality of photonic input/output modules includes a module substrate and a plurality of photonic chip pods disposed on the module substrate. Each photonic chip pod includes a pod substrate with a photonic input/output chiplet and a gearbox chiplet attached to the pod substrate. The photonic input/output chiplet includes a parallel electrical interface, a photonic interface, and a plurality of optical macros implemented between the photonic interface and the parallel electrical interface. The gearbox chiplet electrically connects with the parallel electrical interface of the photonic input/output chiplet and a serial electrical interface of the network switch chip. The gearbox chiplet converts between the parallel electrical interface of the photonic input/output chiplet and the serial electrical interface of the network switch chip.

First claim

What is claimed is:

1 . A photonic chip pod, comprising:
a substrate; a photonic input/output chiplet attached to the substrate, the photonic input/output chiplet including a parallel electrical interface, a photonic interface, and a plurality of optical macros implemented between the photonic interface and the parallel electrical interface, the photonic input/output chiplet disposed on the substrate with a first portion of the photonic input/output chiplet overlying the substrate and with a second portion of the photonic input/output chiplet extending beyond an edge of the substrate in a direction away from the edge of the substrate, the second portion of the photonic input/output chiplet including the photonic interface; and a gearbox chiplet attached the substrate in electrical connection with the parallel electrical interface of the photonic input/output chiplet, the gearbox chiplet configured to provide conversion between the parallel electrical interface of the photonic input/output chiplet and a serial electrical interface of another chip.

2 . The photonic chip pod as recited in claim 1 , wherein the substrate is either a 2.5D integration substrate, a silicon interposer substrate, or an optically-enabled wafer-level fanout substrate.

3 . The photonic chip pod as recited in claim 1 , wherein the serial electrical interface of said another chip is either an extra short reach (XSR) serial interface or an ultra short reach (USR) serial interface.

4 . The photonic chip pod as recited in claim 1 , wherein the parallel electrical interface of the photonic input/output chiplet is either an advanced interface bus (AIB) interface or a high-bandwidth interconnect (HBI) interface.

5 . The photonic chip pod as recited in claim 1 , wherein the photonic interface of the photonic input/output chiplet includes a plurality of optical alignment structures configured to respectively receive and position a plurality of optical fibers for respective optically coupling with a plurality of optical grating couplers formed within the photonic input/output chiplet.

6 . The photonic chip pod as recited in claim 1 , wherein each of the plurality of optical macros of the photonic input/output chiplet includes a plurality of optical microring resonators, wherein each optical microring resonator of the plurality of optical microring resonators has an outer diameter of less than or equal to about 10 micrometers.

7 . The photonic chip pod as recited in claim 1 , wherein the second portion of the photonic input/output chiplet extends beyond the edge of the substrate by a distance of about 3 millimeters as measured in a direction perpendicular to the edge of the substrate.

8 . The photonic chip pod as recited in claim 1 , wherein the substrate extends at least about 1 millimeter beyond each outer edge of the first portion of the photonic input/output chiplet.

9 . The photonic chip pod as recited in claim 1 , wherein the substrate extends at least about 1 millimeter beyond each outer edge of the gearbox chiplet.

10 . The photonic chip pod as recited in claim 1 , wherein the gearbox chiplet is positioned about 1 millimeter away from the photonic input/output chiplet.

11 . The photonic chip pod as recited in claim 1 , wherein the photonic input/output chiplet and the gearbox chiplet are the only chiplets attached to the substrate.

12 . The photonic chip pod as recited in claim 1 , further comprising:
a fiber array unit optically coupled to the photonic interface of the photonic input/output chiplet.

13 . The photonic chip pod as recited in claim 12 , wherein the fiber array unit includes a plurality of optical fibers and a mechanical transfer ferrule, wherein a first end of each of the plurality of optical fibers is secured within the mechanical transfer ferrule, and wherein a second end of each of the plurality of optical fibers is secured within the photonic interface of the photonic input/output chiplet.

14 . The photonic chip pod as recited in claim 13 , wherein the fiber array unit has 16 optical fibers.

15 . The photonic chip pod as recited in claim 13 , wherein the fiber array unit has 24 optical fibers.

16 . The photonic chip pod as recited in claim 1 , wherein a surface of the substrate onto which the photonic input/output chiplet and the gearbox chiplet are attached has a surface area of about 132 square millimeters.

17 . The photonic chip pod as recited in claim 16 , wherein the substrate has a length of about 12 millimeters and a width of about 11 millimeters.

18 . The photonic chip pod as recited in claim 1 , wherein a surface of the first portion of the photonic input/output chiplet that overlies the substrate has a surface area of about 54 square millimeters.

19 . The photonic chip pod as recited in claim 1 , wherein a surface of the second portion of the photonic input/output chiplet that extends beyond the edge of the substrate has a surface area of about 27 square millimeters.

20 . The photonic chip pod as recited in claim 5 , wherein each of the plurality of optical alignment structures is a respective v-groove.

Assignees

• Ayar Labs Inc

Inventors

• Stojanovic Vladimir
• Saleh Hugo
• Meade Roy Edward

Classifications

• H04B10/40

  Transceivers · CPC title

• H04L49/351 Primary

  for local area network [LAN], e.g. Ethernet switches · CPC title

• H04Q11/0067

  Provisions for optical access or distribution networks, e.g. Gigabit Ethernet Passive Optical Network (GE-PON), ATM-based Passive Optical Network (A-PON), PON-Ring · CPC title

• H04L49/357

  Fibre channel switches · CPC title

• H04L49/405

  Physical details, e.g. power supply, mechanical construction or backplane of ATM switches · CPC title