Fused memory and arithmetic circuit

Patent metadata

Field	Value
Publication number	US-12567863-B2
Application number	US-202418612278-A
Country	US
Kind code	B2
Filing date	Mar 21, 2024
Priority date	May 20, 2019
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A tile of an FPGA fuses memory and arithmetic circuits. Connections directly between multiple instances of the tile are also available, allowing multiple tiles to be treated as larger memories or arithmetic circuits. By using these connections, referred to as cascade inputs and outputs, the input and output bandwidth of the arithmetic circuit is further increased. The arithmetic unit accesses inputs from a combination of: the switch fabric, the memory circuit, a second memory circuit of the tile, and a cascade input. In some example embodiments, the routing of the connections on the tile is based on post-fabrication configuration. In one configuration, all connections are used by the memory circuit, allowing for higher bandwidth in writing or reading the memory. In another configuration, all connections are used by the arithmetic circuit.

First claim

What is claimed is:

1 . A tile of a field programmable gate array (FPGA) comprising:
an arithmetic circuit; and a memory circuit comprising:
a memory;
a read multiplexer;
a write multiplexer; and
an input block configured to:
receive first inputs from the arithmetic circuit, second inputs from a routing fabric of the FPGA, and control signals from the routing fabric of the FPGA; and
based on the control signals and at least a portion of the first inputs and the second inputs, provide inputs to the memory, the read multiplexer, and the write multiplexer.

2 . The tile of claim 1 , wherein the input block is further configured to receive memory cascade inputs from a second tile of the FPGA.

3 . The tile of claim 2 , wherein the input block is further configured to receive reverse memory cascade inputs from a third tile of the FPGA.

4 . The tile of claim 1 , wherein the input block is further configured to provide memory cascade outputs to a second tile of the FPGA without using the routing fabric.

5 . The tile of claim 4 , wherein the input block is further configured to provide reverse memory cascade outputs to a third tile of the FPGA without using the routing fabric.

6 . The tile of claim 1 , wherein the inputs provided by the input block to the write multiplexer comprise a write address, a write enable signal, and data.

7 . The tile of claim 6 , wherein the write address is selected from the control signals or memory cascade inputs based on an input select signal.

8 . The tile of claim 6 , wherein the write enable signal is selected from the control signals or memory cascade inputs based on an input select signal.

9 . The tile of claim 1 , wherein the inputs provided to the memory comprise a write address and a read enable signal.

10 . The tile of claim 1 , wherein the memory is configured to provide data to the read multiplexer.

11 . The tile of claim 10 , wherein the data provided by the memory is selected, based on a read enable signal, from data provided by the write multiplexer and data read from the memory.

12 . The tile of claim 1 , wherein the read multiplexer generates outputs to the routing fabric and to the arithmetic circuit.

13 . The tile of claim 1 , wherein the arithmetic circuit is enabled to read and write data to/from the memory circuit at intra-tile communication speeds instead of slower routing fabric speeds.

14 . A method comprising:
receiving, by an input block of a tile of a field programmable gate array (FPGA), first inputs from an arithmetic circuit of the tile, second inputs from a routing fabric of the FPGA, and control signals from the routing fabric of the FPGA; and based on the control signals and at least a portion of the first inputs and the second inputs, providing, by the input block, inputs to a memory of the tile, a read multiplexer of the tile, and a write multiplexer of the tile.

15 . The method of claim 14 , further comprising receiving, by the input block, memory cascade inputs from a second tile of the FPGA.

16 . The method of claim 15 , further comprising receiving, by the input block, reverse memory cascade inputs from a third tile of the FPGA.

17 . The method of claim 14 , further comprising providing, by the input block, memory cascade outputs to a second tile of the FPGA without using the routing fabric.

18 . A non-transitory machine-readable medium containing instructions that, when executed by one or more processors, cause the one or more processors to configure a tile of a field programmable gate array (FPGA) to comprise:
an arithmetic circuit; and a memory circuit comprising:
a memory;
a read multiplexer;
a write multiplexer; and
an input block configured to:
receive first inputs from the arithmetic circuit, second inputs from a routing fabric of the FPGA, and control signals from the routing fabric of the FPGA; and
based on the control signals and at least a portion of the first inputs and the second inputs, provide inputs to the memory, the read multiplexer, and the write multiplexer.

19 . The non-transitory machine-readable medium of claim 18 , wherein the input block is further configured to receive memory cascade inputs from a second tile of the FPGA.

20 . The non-transitory machine-readable medium of claim 19 , wherein the input block is further configured to receive reverse memory cascade inputs from a third tile of the FPGA.

Assignees

• Achronix Semiconductor Corp

Inventors

• Pugh Daniel
• Nijssen Raymond
• Fitton Michael Philip

Classifications

• H03K19/17744 Primary

  for input/output signals · CPC title

• H03K19/17724

  Structural details of logic blocks · CPC title

• H03K19/1776 Primary

  for memories · CPC title

• H03K19/173

  using elementary logic circuits as components · CPC title

• H03K19/17796

  for physical disposition of blocks · CPC title