Nonvolatile memory devices and methods of operating the nonvolatile memory devices

Patent metadata

Field	Value
Publication number	US-12567466-B2
Application number	US-202318468345-A
Country	US
Kind code	B2
Filing date	Sep 15, 2023
Priority date	Dec 20, 2022
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

Provided is a method of operating a nonvolatile memory device including a voltage generator, the method including calculating a difference between a voltage level of a first word line node and a voltage level of a second word line node, changing a first reference voltage level of the voltage generator to a second reference voltage level based on the difference between the voltage levels, and determining a target voltage level based on any one of the first reference voltage level and the second reference voltage level. The first word line node may be closer from an output terminal of the voltage generator than the second word line node.

First claim

What is claimed is:

1 . A method of operating a nonvolatile memory device including a voltage generator, the method comprising:
calculating a difference between a first voltage level of a first word line node and a second voltage level of a second word line node; changing a first reference voltage level of the voltage generator to a second reference voltage level based on the difference between the first voltage level of the first word line node and the second voltage level of the second word line node; and determining a target voltage level based on any one of the first reference voltage level and the second reference voltage level, wherein the first word line node is closer from an output terminal of the voltage generator than the second word line node.

2 . The method of claim 1 , further comprising performing any one of program, read, program verify, and erase verify on a nonvolatile memory of the nonvolatile memory device based on the target voltage level.

3 . The method of claim 1 , wherein the changing of the first reference voltage level to the second reference voltage level comprises:
generating a reference compensation level based on the difference between the first voltage level of the first word line node and the second voltage level of the second word line node; and generating the second reference voltage level by adding the first reference voltage level and the reference compensation level.

4 . The method of claim 1 , wherein the changing of the first reference voltage level to the second reference voltage level comprises:
generating a reference compensation level based on the difference between the first voltage level of the first word line node and the second voltage level of the second word line node; converting the reference compensation level into a first digital code; generating a second digital code by adding the first digital code and the first reference voltage level; and determining a third voltage level corresponding to the second digital code as the second reference voltage level.

5 . The method of claim 4 , further comprising:
determining a duration of the target voltage level based on the first digital code; and applying the target voltage level for the duration.

6 . The method of claim 1 , wherein the determining of the target voltage level based on any one of the first reference voltage level and the second reference voltage level comprises determining the target voltage level based on the second reference voltage level when a difference between the first reference voltage level and the second reference voltage level is greater than or equal to a threshold value.

7 . The method of claim 1 , wherein the determining of the target voltage level based on any one of the first reference voltage level and the second reference voltage level comprises determining the target voltage level based on the first reference voltage level when a difference between the first reference voltage level and the second reference voltage level is less than a threshold value.

8 . The method of claim 1 , wherein
the first word line node is the output terminal of the voltage generator, and the second word line node is a node on a word line separated from the output terminal of the voltage generator by a preset distance or more.

9 . The method of claim 1 , wherein
the first word line node is a node on a word line separated by a preset distance or more from the output terminal of the voltage generator, and the second word line node is further away from the output terminal of the voltage generator than the first word line node.

10 . A method of operating a nonvolatile memory device including a voltage generator, the method comprising:
calculating a difference between a first voltage level of a first bit line node and a second voltage level of a second bit line node; changing a first reference voltage level of the voltage generator to a second reference voltage level based on the difference between the first voltage level of the first bit line node and the second voltage level of the second bit line node; and determining a target voltage level based on any one of the first reference voltage level and the second reference voltage level, wherein the first bit line node is closer from an output terminal of the voltage generator than the second bit line node.

11 . The method of claim 10 , further comprising performing any one of program, read, program verify, and erase verify on a nonvolatile memory of the nonvolatile memory device based on the target voltage level.

12 . The method of claim 10 , wherein the changing of the first reference voltage level to the second reference voltage level comprises:
generating a reference compensation level based on the difference between the first voltage level of the first bit line node and the second voltage level of the second bit line node; and generating the second reference voltage level by adding the first reference voltage level and the reference compensation level.

13 . The method of claim 10 , wherein the changing of the first reference voltage level to the second reference voltage level comprises:
generating a reference compensation level based on the difference between the first voltage level of the first bit line node and the second voltage level of the second bit line node; converting the reference compensation level into a first digital code; generating a second digital code by adding the first digital code and the first reference voltage level; and determining a third voltage level corresponding to the second digital code as the second reference voltage level.

14 . The method of claim 13 , further comprising:
determining a duration of the target voltage level based on the first digital code; and applying the target voltage level for the duration.

15 . A nonvolatile memory device including a switch, a voltage subtractor, and a voltage adder, the nonvolatile memory device comprising:
a memory cell array including memory cells and select word lines coupled to the memory cells; a control logic configured to control the voltage subtractor to calculate a difference between a first voltage level of a first word line node and a second voltage level of a second word line node, control the voltage adder to change a first reference voltage level to a second reference voltage level based on the difference between the first voltage level of the first word line node and the second voltage level of the second word line node, and control the switch to determine a target voltage level based on any one of the first reference voltage level and the second reference voltage level; and a voltage generator configured to generate the target voltage level, wherein the first word line node and the second word line node are nodes on a selected word line, and the first word line node is closer from an output terminal of the voltage generator than the second word line node.

16 . The nonvolatile memory device of claim 15 , wherein the control logic is further configured to control performing any one of program, read, program verify, and erase verify on the memory cell array based on the target voltage level.

17 . The nonvolatile memory device of claim 15 , wherein that the control logic is configured to control the voltage adder to change the first reference voltage level to the second reference voltage level includes that the control logic is configured to control the voltage subtractor to generate a reference compensation level based on the difference between the first voltage level o

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Philkyu
• Kim Chihyun
• Park Junehong
• Yoon Jayang
• Yoon Chiweon
• Lee Dojeon

Classifications

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/30 Primary

  Power supply circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title