Storage device

Patent metadata

Field	Value
Publication number	US-12567448-B2
Application number	US-202318149701-A
Country	US
Kind code	B2
Filing date	Jan 4, 2023
Priority date	Jan 14, 2022
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

The present disclosure provides a storage device, including: at least one first storage region, at least one drive module, and at least one amplification module. The drive module is arranged on both sides of each of the first storage regions in a word line direction, and the amplification module is arranged on both sides of each of the first storage regions in a bit line direction. Each of the first storage regions includes at least one hybrid storage block arranged side by side in the word line direction and configured to store data and an on die error correcting code (OD-ECC).

First claim

The invention claimed is:

1 . A storage device, comprising:
first storage regions, word lines and bit lines; and a drive module arranged on each side of each of the first storage regions in a word line direction, and an amplification module arranged on each side of each of the first storage regions in a bit line direction, wherein each of the first storage regions comprises at least one hybrid storage block arranged side by side in the word line direction and configured to store data and an on die error correcting code; and a second storage region; wherein, the drive module is arranged on both sides of the second storage region in the word line direction, and the amplification module is arranged on both sides of the second storage region in the bit line direction; and the second storage region is provided with a system error correcting code subregion, and the system error correcting code subregion comprises at least one system error correcting code storage block arranged side by side in the word line direction and configured to store a system error correcting code.

2 . The storage device according to claim 1 , wherein the first storage regions are arranged side by side in the word line direction, and the second storage region is located between two of the first storage regions; and
the drive module is arranged between any adjacent first storage regions of the first storage regions, and the drive module is arranged between the second storage region and a first storage region of the first storage regions arranged adjacently.

3 . The storage device according to claim 1 , wherein the second storage region is further provided with a first redundancy subregion and a second redundancy subregion; wherein,
the first redundancy subregion comprises first redundancy storage block arranged side by side on a word line, and the second redundancy subregion comprises at least one second redundancy storage block arranged side by side on the word line; wherein, the first redundancy storage block is configured to store the system error correcting code, and the second redundancy storage block is configured to store the data and the on die error correcting code.

4 . The storage device according to claim 3 , wherein the second storage region further comprises three first virtual storage blocks; and
a system error correcting code region is located between two of the first virtual storage blocks, and the first redundancy subregion and the second redundancy subregion arranged continuously are located between two of the first virtual storage blocks.

5 . The storage device according to claim 4 , wherein a first storage region of the first storage regions further comprises two second virtual storage blocks; wherein, the at least one hybrid storage block arranged continuously is located between two of the second virtual storage blocks.

6 . The storage device according to claim 1 , wherein a hybrid storage block of the at least one hybrid storage block comprises a plurality of first storage structures arranged side by side in the word line direction;
wherein, each of the first storage structures comprises a first substructure and a second substructure arranged side by side in the word line direction, wherein the first substructure is configured to store the data and the on die error correcting code, and the second substructure is configured to store the data and the on die error correcting code.

7 . The storage device according to claim 6 , wherein the first substructure comprises a plurality of memory cells, nine bit lines arranged continuously, and a plurality of word lines arranged continuously; wherein, each of the memory cells comprises a transistor and a capacitor, and a source of the transistor is connected to the capacitor; each of the bit lines is connected to a drain of the transistor arranged in the bit line direction; and each of the word lines is connected to a gate of the transistor arranged in the word line direction;
wherein, the word line direction is perpendicular to the bit line direction; the nine bit lines are controlled by a same column selection line; among the nine bit lines arranged continuously, one line bit located on an edge is called a first error correcting code bit line, and each of remaining eight bit lines arranged continuously is called a first data bit line; the memory cell connected to the first data bit line is configured to store the data, and the memory cell connected to the first error correcting code bit line is configured to store the on die error correcting code.

8 . The storage device according to claim 7 , wherein the second substructure comprises a plurality of memory cells, nine bit lines arranged continuously, and a plurality of word lines arranged continuously; wherein, each of the bit lines is connected to a drain of a transistor arranged in the bit line direction; and each of the word lines is connected to a gate of the transistor arranged in the word line direction;
wherein, the word line direction is perpendicular to the bit line direction; the nine bit lines are controlled by the same column selection line; among the nine bit lines arranged continuously, one line bit located on an edge is called a second error correcting code bit line, and each of remaining eight bit lines arranged continuously is called a second data bit line; the memory cell connected to the second data bit line is configured to store the data, and the memory cell connected to the second error correcting code bit line is configured to store the on die error correcting code; and the first error correcting code bit line and the second error correcting code bit line are arranged adjacently.

9 . The storage device according to claim 8 , wherein the amplification module comprises a plurality of sense amplifiers; wherein,
the first error correcting code bit line in the first substructure is connected to a first sense amplifier; the second error correcting code bit line in the second substructure is connected to a second sense amplifier; and the first sense amplifier and the second sense amplifier are arranged on different sides of the first substructure in the bit line direction.

10 . The storage device according to claim 9 , wherein the sense amplifiers connected to any adjacent two of the bit lines in the first substructure are marked as a third sense amplifier and a fourth sense amplifier, wherein the third sense amplifier and the fourth sense amplifier are arranged on the different sides of the first substructure in the bit line direction; and
the sense amplifiers connected to any adjacent two of the bit lines in the second substructure are marked as a fifth sense amplifier and a sixth sense amplifier, wherein the fifth sense amplifier and the sixth sense amplifier are arranged on different sides of the second substructure in the bit line direction.

11 . The storage device according to claim 6 , wherein a system error correcting code storage block comprises a plurality of second storage structures arranged side by side; wherein,
the second storage structure comprises a plurality of memory cells, eight bit lines arranged continuously, and a plurality of word lines arranged continuously; wherein, each of the memory cells comprises a transistor and a capacitor, and a source of the transistor is connected to the capacitor; each of the eight bit lines arranged continuously is called a third data bit line; each of the third data bit lines is connected to a drain of the transistor arranged in the bit line direction; each of the word lines is connected to a gate of the transistor arranged in the word line direction; the word line direction is perpendicular to the bit line direction;

Assignees

• Changxin Memory Tech Inc

Inventors

• Na Onegyun
• Pan Yusheng

Classifications

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C2029/0411

  Online error correction · CPC title

• G11C29/70

  Masking faults in memories by using spares or by reconfiguring · CPC title

• G11C11/4097

  Bit-line organisation, e.g. bit-line layout, folded bit lines · CPC title

• G11C7/18

  Bit line organisation; Bit line lay-out · CPC title