Gate driving panel circuit and display device

Patent metadata

Field	Value
Publication number	US-12567378-B2
Application number	US-202519030576-A
Country	US
Kind code	B2
Filing date	Jan 17, 2025
Priority date	Feb 28, 2023
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A display device can include a substrate including a display area in which one or more images are displayed and a non-display area different from the display area, and a gate driving panel circuit configured to output a plurality of gate signals to a plurality of gate lines arranged in the display area. The gate driving panel circuit can include an output buffer block comprising a plurality of output buffers, wherein each of the plurality of output buffers comprising a pull-up transistor and a pull-down transistor.

First claim

What is claimed is:

1 . A display device comprising:
a substrate including a display area in which one or more images are displayed and a non-display area different from the display area; and a gate driving panel circuit configured to output a plurality of gate signals to a plurality of gate lines arranged in the display area, wherein the gate driving panel circuit comprises: an output buffer block comprising a plurality of output buffers, each of the plurality of output buffers comprising a pull-up transistor and a pull-down transistor; and a logic block configured to control respective voltages of a Q node and a QB node electrically connected to the output buffer block, wherein the Q node is electrically connected in common to a gate node of the pull-up transistor of each of the plurality of output buffers, and the QB node is electrically connected in common to a gate node of the pull-down transistor of each of the plurality of output buffers, and wherein among the plurality of output buffers, a capacitance between a source node and a gate node of the pull-up transistor of at least one output buffer is different from a capacitance between a source node and a gate node of the pull-up transistor of another output buffer.

2 . The display device of claim 1 , wherein the plurality of output buffers comprises:
a first output buffer configured to output a first gate signal among the plurality of gate signals, and comprising a first pull-up transistor and a first pull-down transistor for outputting the first gate signal to a first gate line among the plurality of gate lines; and a second output buffer configured to output a second gate signal among the plurality of gate signals, and comprising a second pull-up transistor and a second pull-down transistor for outputting the second gate signal to a second gate line among the plurality of gate lines.

3 . The display device of claim 2 , further comprising:
a first clock signal line disposed in the non-display area and delivering a first clock signal to the first output buffer; a second clock signal line disposed in the non-display area and delivering a second clock signal to the second output buffer; at least one gate high voltage line disposed in the non-display area and delivering at least one gate high voltage to the gate driving panel circuit; and at least one gate low voltage line disposed in the non-display area and delivering at least one gate low voltage to the gate driving panel circuit.

4 . The display device of claim 3 , wherein the first clock signal line and the second clock signal line are located further from the display area than the gate driving panel circuit,
wherein the at least one gate high voltage line is located on one side of the gate driving panel circuit, and wherein the at least one gate low voltage line is located on the other side of the gate driving panel circuit.

5 . The display device of claim 4 , wherein the at least one gate high voltage line is disposed between a clock signal line area where the first clock signal line and the second clock signal line are disposed and the gate driving panel circuit,
wherein the at least one gate low voltage line is disposed between the gate driving panel circuit and the display area, wherein the at least one gate high voltage is delivered to the logic block of the gate driving panel circuit, and wherein the at least one gate low voltage is delivered to the output buffer block and the logic block of the gate driving panel circuit.

6 . The display device of claim 2 , wherein the plurality of output buffers further comprises a third output buffer configured to output a carry signal, and comprising a third pull-up transistor and a third pull-down transistor for outputting the carry signal.

7 . The display device of claim 2 , further comprising a plurality of subpixels arranged in the display area,
wherein both the first gate signal and the second gate signal are supplied to a first subpixel among the plurality of subpixels.

8 . The display device of claim 2 , further comprising a plurality of subpixels arranged in the display area,
wherein the first gate signal is supplied to a first subpixel among the plurality of subpixels, and the second gate signal is supplied to a second subpixel different from the first subpixel among the plurality of subpixels.

9 . The display device of claim 1 , further comprising:
an emission layer in the display area; a cathode electrode disposed on the emission layer and extending from the display area to the non-display area; and an encapsulation layer disposed on the cathode electrode and extending from the display area to the non-display area, wherein the encapsulation layer extends further outward than the cathode electrode, and wherein the cathode electrode overlaps with all or at least a portion of the gate driving panel circuit.

10 . The display device of claim 9 , further comprising an overcoat layer disposed between the gate driving panel circuit and the cathode electrode,
wherein the overcoat layer has at least one trench in the non-display area.

11 . The display device of claim 10 , wherein the gate driving panel circuit is disposed further outward than the at least one trench.

12 . The display device of claim 1 , further comprising a real-time sensing control block configured to control voltages of the Q node and the QB node during a blank period between active periods.

13 . The display device of claim 12 , wherein the real-time sensing control block is closer to a control block than to the output buffer block.

14 . The display device of claim 12 , wherein the real-time sensing control block comprises a sensing control capacitor,
wherein the sensing control capacitor has a capacitance different from a capacitance between the source node and the gate node of each of the pull-up transistors of the plurality of output buffers.

15 . The display device of claim 1 , further comprising a dummy gate driving panel circuit having the same structure as the gate driving panel circuit and not connected to the plurality of gate lines.

16 . The display device of claim 15 , wherein the dummy gate driving panel circuit is disposed in all or part of a plurality of corner areas in the non-display area.

17 . The display device of claim 1 , further comprising an electrostatic discharge component disposed in the non-display area, wherein the electrostatic discharge component includes an electrostatic discharge circuit or an electrostatic discharge pattern.

18 . The display device of claim 17 , wherein a cathode electrode overlaps at least a portion of the electrostatic discharge component.

19 . The display device of claim 1 , wherein a portion of a high level voltage section of a first gate signal and a portion of a high level voltage section of a second gate signal among the plurality of gate signals overlap in time.

20 . The display device of claim 1 , wherein the gate driving panel circuit is disposed in a gate driving panel circuit area included in the non-display area.

Assignees

• Lg Display Co Ltd

Inventors

• Jang Min-June
• Son Miyoung
• Shin Hongjae

Classifications

• G09G2310/0291

  Details of output amplifiers or buffers arranged for use in a driving circuit · CPC title

• G09G2300/0861

  with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title