Display panel having pixel circuits and display apparatus

Patent metadata

Field	Value
Publication number	US-12567375-B2
Application number	US-202218692042-A
Country	US
Kind code	B2
Filing date	Sep 27, 2022
Priority date	Sep 27, 2022
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A display panel includes pixel circuits, first shift register(s), second shift register(s), third shift register(s), and fourth shift register(s). A pixel circuit includes a driving transistor, a bias sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a leakage prevention sub-circuit, a reset sub-circuit, and a light-emission control sub-circuit. The bias sub-circuit is electrically connected to a first shift register, which transmits a first scanning signal to the bias sub-circuit. The data writing and compensation sub-circuits are electrically connected to a second shift register, which transmits a second scanning signal to the data writing and compensation sub-circuits. The leakage prevention sub-circuit is electrically connected to a third shift register, which transmits a third scanning signal to the leakage prevention sub-circuit. The light-emission control sub-circuit is electrically connected to a fourth shift register, which transmits a fourth scanning signal to the light-emission control sub-circuit.

First claim

What is claimed is:

1 . A display panel, comprising:
a plurality of pixel circuits, arranged in multiple rows and multiple columns; a plurality of light-emitting devices; at least one first shift register, a first shift register being correspondingly connected to at least one row of pixel circuits, and the first shift register being configured to transmit a first scanning signal to the at least one row of pixel circuits correspondingly connected thereto; at least one second shift register, a second shift register being correspondingly connected to a row of pixel circuits, and the second shift register being configured to transmit a second scanning signal to the row of pixel circuits correspondingly connected thereto; at least one third shift register, a third shift register being correspondingly connected to at least one row of pixel circuits, and the third shift register being configured to transmit a third scanning signal to the at least one row of pixel circuits correspondingly connected thereto; and at least one fourth shift register, a fourth shift register being correspondingly connected to at least one row of pixel circuits, and the fourth shift register being configured to transmit a fourth scanning signal to the at least one row of pixel circuits correspondingly connected thereto; wherein a pixel circuit of the plurality of pixel circuits includes a driving transistor, a bias sub-circuit, a data writing sub-circuit, a compensation sub-circuit, a leakage prevention sub-circuit, a reset sub-circuit, and a light-emission control sub-circuit, wherein the bias sub-circuit is electrically connected to the first shift register, a reference voltage terminal and a source of the driving transistor, and is configured to, under control of the first scanning signal, transmit a reference voltage from the reference voltage terminal to the source of the driving transistor; the data writing sub-circuit is electrically connected to the second shift register, a data signal terminal and the source of the driving transistor, and is configured to, under control of the second scanning signal, transmit a data signal from the data signal terminal to the source of the driving transistor; the compensation sub-circuit is electrically connected to the second shift register, a drain of the driving transistor and a first node, and is configured to, under control of the second scanning signal, transmit a compensated data signal to the first node; the leakage prevention sub-circuit is electrically connected to the third shift register, the first node and a gate of the driving transistor, and is configured to, under control of the third scanning signal, cause a connection to be formed between the first node and the gate of the driving transistor; the reset sub-circuit is electrically connected to the first node and a light-emitting device, electrically connected to the pixel circuit, of the plurality light-emitting devices, and is configured to reset a voltage of the first node and a voltage of the light-emitting device; and the light-emission control sub-circuit is electrically connected to the fourth shift register, a first voltage signal terminal, the driving transistor and the light-emitting device, and is configured to, under control of the fourth scanning signal, cause a path to be formed between the driving transistor and the light-emission control sub-circuit to transmit a driving current to the light-emitting device; wherein a row of pixel circuits is correspondingly connected to one first shift register, two third shift registers and one fourth shift register; and the row of pixel circuits has opposite two sides along a first direction, and the first direction is a direction in which the row of pixel circuits is arranged, wherein the fourth shift register and one of the third shift registers are located at one side of the two sides, and the first shift register and an other one of the third shift registers are located at an other side of the two sides.

2 . The display panel according to claim 1 , wherein at least one of the first shift register and the third shift register is located at the one side of the two sides.

3 . The display panel according to claim 1 , wherein a row of pixel circuits is correspondingly connected to two second shift registers; one of the second shift registers is located at the one side of the opposite two sides of the row of pixel circuits along the first direction, and is adjacent to the row of pixel circuits; and an other one of the second shift registers is located at the other side of the opposite two sides of the row of pixel circuits along the first direction, and is adjacent to the row of pixel circuits.

4 . The display panel according to claim 1 , wherein the first shift register, the third shift register and the fourth shift register each include twelve transistors and three capacitors, and the second shift register includes eight transistors and two capacitors; and
the display panel further comprises: a first clock signal line, a second clock signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, a sixth clock signal line, a seventh clock signal line, an eighth clock signal line, a ninth clock signal line, and a tenth clock signal line; a first low-voltage signal line, a second low-voltage signal line, a third low-voltage signal line, a fourth low-voltage signal line, a fifth low-voltage signal line, a sixth low-voltage signal line, and a seventh low-voltage signal line; a first high-voltage signal line, a second high-voltage signal line, a third high-voltage signal line, and a fourth high-voltage signal line; and a first start signal line, a second start signal line, a third start signal line, and a fourth start signal line, wherein the first shift register is electrically connected to the first low-voltage signal line, the first clock signal line, the second clock signal line, the first start signal line, the first high-voltage signal line, and the second low-voltage signal line; the second shift register is electrically connected to two of the third clock signal line, the fourth clock signal line, the fifth clock signal line, and the sixth clock signal line, and is electrically connected to the third low-voltage signal line, the second start signal line and the second high-voltage signal line; the third shift register is electrically connected to the fourth low-voltage signal line, the seventh clock signal line, the eighth clock signal line, the third start signal line, the third high-voltage signal line, and the fifth low-voltage signal line; and the fourth shift register is electrically connected to the sixth low-voltage signal line, the ninth clock signal line, the tenth clock signal line, the fourth start signal line, the fourth high-voltage signal line, and the seventh low-voltage signal line.

5 . The display panel according to claim 4 , wherein
the two sides include a side at which the fourth shift register is located; and at the side and along a direction that is in the first direction and from the side to the plurality of pixel circuits, a sixth low-voltage signal line, a ninth clock signal line, a tenth clock signal line, a fourth start signal line, a fourth high-voltage signal line, a seventh low-voltage signal line, a fourth low-voltage signal line, a seventh clock signal line, an eighth clock signal line, a third start signal line, a third high-voltage signal line, a fifth low-voltage signal line, a third low-voltage signal line, a third clock signal line, a fourth clock signal line, a fifth clock signal line, a sixth clock signal line, a second start signal line, and a second high-voltage signal line are arranged in sequence; and the two sides include a side at which the first shift register is located; and at the side a

Assignees

• Boe Technology Group Co Ltd

Inventors

• Liu Libin
• Feng Yu
• Shi Shiming
• Wang Dawei
• Qiu Haijun
• Wang Jingquan
• Yao Xing

Classifications

• G09G3/3233

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G3/32

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G3/30

  using electroluminescent panels · CPC title

• G09G2310/061

  for resetting or blanking · CPC title

• G09G2330/021

  Power management, e.g. power saving · CPC title