Array substrate and display panel

Patent metadata

Field	Value
Publication number	US-12567372-B2
Application number	US-202418992729-A
Country	US
Kind code	B2
Filing date	Aug 13, 2024
Priority date	Sep 25, 2023
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

In an array substrate, a control electrode of a driving transistor, a second electrode of a compensation transistor and a second electrode of a first reset transistor are electrically connected to a first conductive connection portion, and a first electrode of the driving transistor and a second electrode of a data writing transistor are electrically connected to a second conductive connection portion. An orthographic projection of a first conductive portion of the first conductive connection portion overlaps with an orthographic projection of a first scan signal line, and overlaps with an orthographic projection of a second scan signal line. A first shielding layer includes a first shielding pattern; in a thickness direction of the substrate, the first shielding pattern is located between the first scan signal line and the first conductive portion, and/or the first shielding pattern is located between the second scan signal line and the first conductive portion.

First claim

What is claimed is:

1 . An array substrate, comprising a substrate and a driving circuit layer located on the substrate, wherein the driving circuit layer includes:
a plurality of pixel driving circuits located on a side of the substrate and arranged in multiple rows and multiple columns, wherein
a pixel driving circuit in the plurality of pixel driving circuits includes a first reset transistor, a compensation transistor, a driving transistor, a data writing transistor, a first conductive connection portion and a second conductive connection portion; and
a control electrode of the driving transistor, a second electrode of the compensation transistor and a second electrode of the first reset transistor are all electrically connected to the first conductive connection portion, and a first electrode of the driving transistor and a second electrode of the data writing transistor are all electrically connected to the second conductive connection portion;
a plurality of first scan signal lines located on the side of the substrate, wherein the plurality of first scan signal lines all extend in a row direction and are arranged in sequence in a column direction, and a first scan signal line is electrically connected to control electrodes of data writing transistors in a row of pixel driving circuits; and an orthographic projection of a first conductive portion of the first conductive connection portion on the substrate overlaps with an orthographic projection of the first scan signal line on the substrate; a plurality of second scan signal lines located on the side of the substrate, wherein the plurality of second scan signal lines all extend in the row direction and are arranged in sequence in the column direction, and a second scan signal line is electrically connected to control electrodes of compensation transistors in the row of pixel driving circuits; and the orthographic projection of the first conductive portion of the first conductive connection portion on the substrate overlaps with an orthographic projection of the second scan signal line on the substrate; and a first shielding layer configured to have a constant voltage signal, wherein the first shielding layer includes a first shielding pattern; in a thickness direction of the substrate, the first shielding pattern is located between the first scan signal line and the first conductive portion; and/or in the thickness direction of the substrate, the first shielding pattern is located between the second scan signal line and the first conductive portion.

2 . The array substrate according to claim 1 , wherein the driving circuit layer includes:
a semiconductor layer located on the substrate, wherein the semiconductor layer includes a first electrode and a second electrode of the first reset transistor, a first electrode and a second electrode of the compensation transistor, a first electrode and a second electrode of the driving transistor, and a first electrode and a second electrode of the data writing transistor; a first gate metal layer located on a side of the semiconductor layer away from the substrate, wherein the first gate metal layer includes a control electrode of the first reset transistor, a control electrode of the compensation transistor, a control electrode of the driving transistor, and a control electrode of the data writing transistor; a second gate metal layer located on a side of the first gate metal layer away from the semiconductor layer; and a first wire metal layer located on a side of the second gate metal layer away from the first gate metal layer, wherein the first wire metal layer includes the first scan signal line and the second scan signal line.

3 . The array substrate according to claim 2 , wherein the first conductive portion is located in the semiconductor layer; an end of the first conductive portion is electrically connected to the second electrode of the first reset transistor, and another end of the first conductive portion is electrically connected to the control electrode of the driving transistor and the second electrode of the compensation transistor;
the first conductive portion includes a first conductive sub-portion and a second conductive sub-portion that are connected; an orthographic projection of the first conductive sub-portion on the substrate overlaps with the orthographic projection of the first scan signal line on the substrate, and the orthographic projection of the first conductive sub-portion on the substrate is within borders of an orthographic projection of the first shielding pattern on the substrate; and/or an orthographic projection of the second conductive sub-portion on the substrate overlaps with the orthographic projection of the second scan signal line on the substrate, and the orthographic projection of the second conductive sub-portion on the substrate is within the borders of the orthographic projection of the first shielding pattern on the substrate.

4 . The array substrate according to claim 3 , wherein the first conductive portion further includes a third conductive sub-portion; an end of the third conductive sub-portion is electrically connected to the first conductive sub-portion, and another end of the third conductive sub-portion is electrically connected to the second conductive sub-portion; and
an orthographic projection of the third conductive sub-portion on the substrate is within the borders of the orthographic projection of the first shielding pattern on the substrate.

5 . The array substrate according to claim 3 , wherein in the column direction, the first shielding pattern includes a first edge and a second edge, and the first edge is located on a side of the second edge away from the driving transistor;
a first minimum distance between an orthographic projection of the first edge on the substrate and an orthographic projection of a side of the first conductive sub-portion away from the second conductive sub-portion on the substrate is greater than or equal to 1 μm; and/or a second minimum distance between an orthographic projection of the second edge on the substrate and an orthographic projection of a side of the second conductive sub-portion away from the first conductive sub-portion on the substrate is greater than or equal to 1 μm.

6 . The array substrate according to claim 3 , wherein in the row direction, a third minimum distance between a border of the orthographic projection of the first shielding pattern on the substrate and a border of the orthographic projection of the first conductive sub-portion on the substrate is greater than or equal to 1 μm; and/or
in the row direction, a fourth minimum distance between a border of the orthographic projection of the first shielding pattern on the substrate and a border of the orthographic projection of the second conductive sub-portion on the substrate is greater than or equal to 1 μm.

7 . The array substrate according to claim 1 , wherein the first shielding pattern includes a first shielding sub-portion extending in the row direction and a second shielding sub-portion extending in the column direction; and
an orthographic projection of the first shielding sub-portion on the substrate overlaps with the orthographic projection of the second scan signal line on the substrate, and an orthographic projection of the second shielding sub-portion on the substrate overlaps with an orthographic projection of the first conductive portion of the first conductive connection portion on the substrate.

8 . The array substrate according to claim 1 , wherein in the column direction, the first reset transistor is located on a side of the first scan signal line away from the second scan signal line; and
an orthographic projection of the first shielding pattern on

Assignees

• Chongqing Boe Display Tech Co Ltd
• Boe Technology Group Co Ltd
• Beijing Boe Technology Dev Co Ltd

Inventors

• Xia Weidi
• Weng Hongtao
• He Xiaoling
• Qiu Yuanyou
• Wang Rui
• Zhan Shuangyuan
• Chen Rui

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G2320/0233

  Improving the luminance or brightness uniformity across the screen · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• H10K59/1216 Primary

  the pixel elements being capacitors · CPC title