Display device

Patent metadata

Field	Value
Publication number	US-12567370-B2
Application number	US-202418931526-A
Country	US
Kind code	B2
Filing date	Oct 30, 2024
Priority date	Oct 30, 2023
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

A display device can include a base, a plurality of pixels arranged in a display area on the base, and a data signal line supplying a data signal to each of the plurality of pixels. Each of the plurality of pixels can include a pixel circuit including a plurality of transistors and a light emitting element driven by the pixel circuit. The pixel circuit can drive the light emitting element to emit light in time division. The first transistor can be connected to the data signal line, among the plurality of transistors including the pixel circuit, can be an oxide transistor.

First claim

What is claimed is:

1 . A display device, comprising:
a base; a plurality of pixels in a display area (DA) on the base; and a data signal line to supply a data signal to each of the plurality of pixels, wherein each of the plurality of pixels includes a pixel circuit having a plurality of transistors and a light emitting element drivable by the pixel circuit, the pixel circuit is configured to drive the light emitting element to emit light according to pulse width modulation, a first transistor is connected to the data signal line, among the plurality of transistors in the pixel circuit, the plurality of transistors include a second transistor to supply current to the light emitting element, the first transistor has a smaller leak current compared to the second transistor, the pixel circuit further includes a storage capacitor to hold a voltage to control the current supplied by the second transistor to the light emitting element, in the second transistor, one of a source terminal and a drain terminal is connected to one of a source terminal and a drain terminal of the first transistor, fourth and fifth transistors among the plurality of transistors in the pixel circuit are polysilicon transistors, the fourth transistor is between a power supply line to supply a power supply voltage (VDDEL) and the second transistor, the fifth transistor is between the light emitting element and the second transistor, the pixel circuit is formed in a circuit layer having a first layer, a second layer, a third layer, a fourth layer, and a fifth layer, the first to fifth layers are stacked in order with the first layer being a bottom layer of the stack and the fifth layer being a top layer of the stack, the first layer is a p-Si layer, the second, fourth, and fifth layers are metal layers, and the third layer is an oxide layer, the first transistor is formed across the second to fourth layers, the second, fourth, and fifth transistors are formed across the first and second layers, and the storage capacitor is formed across the first and second layers.

2 . The display device of claim 1 , wherein
the first transistor is an oxide transistor, and the second transistor is a polysilicon transistor.

3 . The display device of claim 1 , wherein
a third transistor among the plurality of transistors in the pixel circuit is an oxide transistor, and in the third transistor, one of a source terminal and a drain terminal is connected to one of a gate terminal of the second transistor and a terminal of the storage capacitor, and the other of the source terminal and the drain terminal is connected to the other of the source terminal and the drain terminal of the second transistor.

4 . A display device, comprising:
a base; a plurality of pixels in a display area (DA) on the base; and a data signal line to supply a data signal to each of the plurality of pixels, wherein each of the plurality of pixels includes a pixel circuit having a plurality of transistors and a light emitting element drivable by the pixel circuit, the pixel circuit is configured to drive the light emitting element to emit light according to pulse width modulation, a first transistor is connected to the data signal line, among the plurality of transistors in the pixel circuit, the plurality of transistors include a second transistor to supply current to the light emitting element, the pixel circuit is formed in a circuit layer having a first layer, a second layer, a third layer, a fourth layer, and a fifth layer, the first to fifth layers are stacked in order with the first layer being a bottom layer of the stack and the fifth layer being a top layer of the stack, the first transistor is formed across the second to fourth layers, the second transistor is formed across the first and second layers, and the first transistor has a dual-gate structure sandwiched between a first gate electrode in one of the first to fifth layers and a second gate electrode in a different one of the first to fifth layers.

5 . The display device of claim 4 , wherein
a gate signal line, a control signal line, and a power supply line to supply an initialization voltage are formed in the second layer, and the data signal line is formed in the fifth layer.

6 . The display device of claim 4 , wherein
the first layer is a p-Si layer, the second, fourth, and fifth layers are metal layers, and the third layer is an oxide layer.

7 . The display device of claim 4 , wherein
the pixel circuit further includes a storage capacitor to hold a voltage to control the current supplied by the second transistor to the light emitting element, a third transistor among the plurality of transistors in the pixel circuit is an oxide transistor, in the second transistor, one of a source terminal and a drain terminal is connected to one of a source terminal and a drain terminal of the first transistor, and in the third transistor, one of a source terminal and a drain terminal is connected to one of a gate terminal of the second transistor and a terminal of the storage capacitor, and the other of the source terminal and the drain terminal is connected to the other of the source terminal and the drain terminal of the second transistor.

8 . The display device of claim 7 , wherein
the second, fourth, and fifth transistors are formed across the first and second layers, and the storage capacitor is formed across the first and second layers.

9 . A display device, comprising:
a base; a plurality of pixels in a display area (DA) on the base; and a data signal line to supply a data signal to each of the plurality of pixels, wherein each of the plurality of pixels includes a pixel circuit having a plurality of transistors and a light emitting element drivable by the pixel circuit, the pixel circuit is configured to drive the light emitting element to emit light according to pulse width modulation, a first transistor is connected to the data signal line, among the plurality of transistors in the pixel circuit, the plurality of transistors include a second transistor to supply current to the light emitting element, the pixel circuit is formed in a circuit layer having a first layer, a second layer, a third layer, a fourth layer, and a fifth layer, the first to fifth layers are stacked in order with the first layer being a bottom layer of the stack and the fifth layer being a top layer of the stack, the first transistor is formed across the second to fourth layers, the second transistor is formed across the first and second layers, and the first layer is a p-Si layer, the second, fourth, and fifth layers are metal layers, and the third layer is an oxide layer.

10 . The display device of claim 9 , wherein
a gate signal line, a control signal line, and a power supply line to supply an initialization voltage are formed in the second layer, and the data signal line is formed in the fifth layer.

11 . The display device of claim 9 , wherein
the pixel circuit further includes a storage capacitor to hold a voltage to control the current supplied by the second transistor to the light emitting element, a third transistor among the plurality of transistors in the pixel circuit is an oxide transistor, in the second transistor, one of a source terminal and a drain terminal is connected to one of a source terminal and a drain terminal of the first transistor, and in the third transistor, one of a source terminal and a drain terminal is connected to one of a gate terminal of the second transistor and a terminal of the storage capacitor, and the other of the source terminal and the drain terminal is connected to the other of the s

Assignees

• Magnolia White Corp

Inventors

• Morita Tetsuo
• Tabatake Hiroshi

Classifications

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0452

  Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title