Current generator for IDAC for corner independence

Patent metadata

Field	Value
Publication number	US-12566467-B2
Application number	US-202418588989-A
Country	US
Kind code	B2
Filing date	Feb 27, 2024
Priority date	Feb 27, 2024
Publication date	Mar 3, 2026
Grant date	Mar 3, 2026

Abstract

Apparatuses, systems, and methods for improved current generators for IDAC corner independence are provided. An exemplary apparatus may include current generator circuitry and a IDAC. The current generator circuitry is configured to generate a reference current. The IDAC is configured to generate an IDAC current based at least on the reference current. The current generator circuitry may adjust or update the reference current based on a change in temperature and/or process. This results in an adjustment or update in the IDAC current.

First claim

The invention claimed is:

1 . An apparatus comprising:
a current generator circuitry comprising:
an op amp comprising a first input, a second input, and an output, wherein the first input is electrically connected to a reference voltage;
a first FET comprising a first drain, a first gate, and a first source, wherein the first gate is connected to the output of the op amp;
a resistor comprising a first terminal and a second terminal, wherein the first terminal is electrical connected to the first source and to the second input of the op amp, and wherein the second terminal is electrically connected to a ground;
a voltage supply;
a second FET comprising a second drain, a second gate, and a second source, wherein the second drain is electrically connected to a voltage source;
a third FET comprising a third drain, a third gate, and a third source, wherein the third drain is electrically connected to the voltage source, and wherein the third gate is electrically connected to the second gate, the second source, and to the first drain;
an output terminal of the current generator circuitry, wherein the output terminal of the current generator circuitry is electrically connected to the third source; and
an IDAC electrically connected to the output terminal of the current generator circuitry.

2 . The apparatus of claim 1 , wherein the IDAC is configured to generate an IDAC current based at least on a reference current generated by the current generator circuitry.

3 . The apparatus of claim 2 , wherein the current generator circuitry is configured to generate the reference current based on the resistor, and wherein a change in a resistance of the resistor based on a change in temperature is associated with a change in the reference current.

4 . The apparatus of claim 2 , wherein the IDAC is further configured to generate the IDAC current based on a selection signal comprising a plurality of bits.

5 . The apparatus of claim 4 , wherein the plurality of bits comprise 8 bits, and wherein the 8 bits specify to the IDAC a number of current increments to implement in the IDAC current.

6 . The apparatus of claim 2 further comprising PWM circuitry configured to generate a driver signal based at least on the IDAC current.

7 . The apparatus of claim 6 further comprising a SPAD array configured to be driven based at least on the driver signal.

8 . The apparatus of claim 1 , wherein the second FET and the third FET are PMOSFETs.

9 . The apparatus of claim 1 , wherein the first FET is an NMOSFET.

10 . The apparatus of claim 1 , wherein the apparatus is one of a mobile phone, laptop, or augmented reality device.

11 . A method comprising:
generating a first reference current with a current generator circuitry, wherein the current generator circuitry comprises:
an op amp comprising a first input, a second input, and an output, wherein the first input is electrically connected to a reference voltage;
a first FET comprising a first drain, a first gate, and a first source, wherein the first gate is connected to the output of the op amp;
a resistor comprising a first terminal and a second terminal, wherein the first terminal is electrical connected to the first source and to the second input of the op amp, and wherein the second terminal is electrically connected to a ground;
a voltage supply;
a second FET comprising a second drain, a second gate, and a second source, wherein the second drain is electrically connected to a voltage source;
a third FET comprising a third drain, a third gate, and a third source, wherein the third drain is electrically connected to the voltage source, and wherein the third gate is electrically connected to the second gate, the second source, and to the first drain;
an output terminal of the current generator circuitry, wherein the output terminal of the current generator circuitry is electrically connected to the third source;
generating a first IDAC current with an IDAC at a first time based on the first reference current, wherein the IDAC is electrically connected to the output terminal of the current generator circuitry; generating an adjusted reference current with the current generator circuitry at a second time based on a change in temperature; generating an adjusted IDAC current with the IDAC at a second time based on the adjusted reference current.

12 . The method of claim 11 , wherein generating the first reference current is based on the resistor, and wherein generating the adjusted reference current is based on a change in temperature associated with a change in the first reference current.

13 . The method of claim 11 , wherein generating the first IDAC current is based on a selection signal comprising a plurality of bits, and wherein generating the adjusted IDAC current is based on the selection signal.

14 . The method of claim 13 , wherein the plurality of bits comprise 8 bits, and wherein the 8 bits specify to the IDAC a plurality of current increments to implement in the ajusted IDAC current.

15 . The method of claim 14 , each voltage increment of the plurality of current increments is associated with a linear current change.

16 . The method of claim 11 further comprising generating a driver signal with a PWM circuitry based at least on the adjusted IDAC current.

17 . The method of claim 16 , further comprising driving a SPAD array with the driver signal.

18 . The method of claim 11 , wherein the second FET and the third FET are PMOSFETs.

19 . The method of claim 11 , wherein the first PET is an NMOSFET.

20 . The method of claim 11 , wherein the current generator circuitry and the IDAC are in one of a mobile phone, laptop, or augmented reality device.

Assignees

• St Microelectronics Int Nv

Inventors

• Pastorelli Cedric
• Collins Steven

Classifications

• H03M1/74

  Simultaneous conversion · CPC title

• G05F3/262

  using field-effect transistors only · CPC title

• G05F3/26

  Current mirrors · CPC title

• G05F3/205

  Substrate bias-voltage generators (for static stores G11C5/146) · CPC title

• H03M1/089

  of temperature variations · CPC title