Method of manufacturing display device

Patent metadata

Field	Value
Publication number	US-12563959-B2
Application number	US-202318225294-A
Country	US
Kind code	B2
Filing date	Jul 24, 2023
Priority date	Sep 27, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A method of manufacturing a display device includes forming a first amorphous silicon layer on a substrate on which a first area and a second area are defined, forming a mask in the second area on the first amorphous silicon layer, forming a preliminary second amorphous silicon layer on the first amorphous silicon layer and the mask, forming a second amorphous silicon layer by removing a portion of the preliminary second amorphous silicon layer on the mask, removing the mask, and forming a polycrystalline silicon layer by crystallizing the first amorphous silicon layer and the second amorphous silicon layer.

First claim

What is claimed is:

1 . A method of manufacturing a display device, the method comprising:
forming a first amorphous silicon layer on a substrate on which a first area and a second area are defined; forming a mask in the second area on the first amorphous silicon layer; forming a preliminary second amorphous silicon layer on the first amorphous silicon layer and the mask; forming a second amorphous silicon layer by removing a portion of the preliminary second amorphous silicon layer on the mask; removing the mask; and forming a polycrystalline silicon layer by crystallizing the first amorphous silicon layer and the second amorphous silicon layer.

2 . The method of claim 1 , wherein a thickness of the second amorphous silicon layer is less than about 200 Å.

3 . The method of claim 1 , wherein a sum of a thickness of the first amorphous silicon layer and a thickness of the second amorphous silicon layer is in a range of about 300 Å to about 500 Å.

4 . The method of claim 1 , wherein a thickness of the mask is greater than or equal to a thickness of the second amorphous silicon layer.

5 . The method of claim 1 , further comprising:
cleaning the first amorphous silicon layer and the second amorphous silicon layer.

6 . The method of claim 1 , wherein the portion of the preliminary second amorphous silicon layer on the mask and the mask are simultaneously removed.

7 . The method of claim 1 , further comprising:
forming a first polycrystalline silicon pattern and a second polycrystalline silicon pattern in the first area and the second area, respectively, by etching an area of the polycrystalline silicon layer except for areas corresponding to the first area and the second area, respectively.

8 . The method of claim 7 , further comprising:
forming a gate insulating layer on the substrate to cover the first polycrystalline silicon pattern and the second polycrystalline silicon pattern.

9 . The method of claim 8 , further comprising:
forming a first gate electrode overlapping the first polycrystalline silicon pattern and a second gate electrode overlapping the second polycrystalline silicon pattern on the gate insulating layer.

10 . The method of claim 1 , further comprising:
forming a buffer layer on the substrate.

11 . A method of manufacturing a display device, the method comprising:
forming a first amorphous silicon layer on a substrate on which a first area and a second area are defined; forming a photoresist layer on the first amorphous silicon layer; exposing the first amorphous silicon layer overlapping the first area by patterning the photoresist layer; forming a preliminary second amorphous silicon layer on the first amorphous silicon layer and a patterned photoresist layer; forming a second amorphous silicon layer by removing a portion of the preliminary second amorphous silicon layer on the patterned photoresist layer; removing the patterned photoresist layer; and forming a polycrystalline silicon layer by crystallizing the first amorphous silicon layer and the second amorphous silicon layer.

12 . The method of claim 11 , wherein a thickness of the second amorphous silicon layer is less than about 200 Å.

13 . The method of claim 11 , wherein a sum of a thickness of the first amorphous silicon layer and a thickness of the second amorphous silicon layer is in a range of about 300 Å to about 500 Å.

14 . The method of claim 11 , further comprising:
cleaning the first amorphous silicon layer and the second amorphous silicon layer.

15 . The method of claim 11 , wherein the portion of the preliminary second amorphous silicon layer on the photoresist layer and the patterned photoresist layer are simultaneously removed.

16 . The method of claim 11 , further comprising:
forming a first polycrystalline silicon pattern and a second polycrystalline silicon pattern in the first area and the second area, respectively, by etching an area of the polycrystalline silicon layer except for areas corresponding to the first area and the second area, respectively.

17 . The method of claim 16 , further comprising:
forming a gate insulating layer on the substrate to cover the first polycrystalline silicon pattern and the second polycrystalline silicon pattern.

18 . The method of claim 17 , further comprising:
forming a first gate electrode overlapping the first polycrystalline silicon pattern and a second gate electrode overlapping the second polycrystalline silicon pattern on the gate insulating layer.

19 . The method of claim 11 , further comprising:
forming a buffer layer on the substrate.

20 . The method of claim 11 , wherein the photoresist layer is a negative-type photoresist layer.

Assignees

• Samsung Display Co Ltd

Inventors

• Choi Jonghoon
• Okumura Hiroshi

Classifications

• H10K59/1201

  Manufacture or treatment · CPC title

• H10K59/1213

  the pixel elements being TFTs · CPC title

• H10P14/3808

  using laser beams · CPC title

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3454

  Amorphous · CPC title