Display substrate and display apparatus

Patent metadata

Field	Value
Publication number	US-12563917-B2
Application number	US-202117771659-A
Country	US
Kind code	B2
Filing date	Jun 15, 2021
Priority date	Jun 18, 2020
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

The present disclosure provides a display substrate and a display apparatus. The display substrate has a display region, and the display substrate includes a base substrate and a plurality of gate lines and a plurality of data lines on the base substrate; the plurality of gate lines and the plurality of data lines are arranged to cross each other to define a plurality of pixel regions, and a pixel unit is arranged in a pixel region of the plurality of pixel regions; each pixel unit includes a thin-film transistor and a light-emitting device in the display region; the display substrate further comprises a plurality of fan-out traces in the display region, wherein each fan-out trace of the plurality of fan-out traces is electrically connected to a data line corresponding to the fan-out trace, and is arranged in a different layer from the date lines and the gate lines.

First claim

The invention claimed is:

1 . A display substrate, having a display region, the display substrate comprising: a base substrate, and a plurality of gate lines and a plurality of data lines on the base substrate; the plurality of gate lines and the plurality of data lines on the base substrate being arranged to cross each other to define a plurality of pixel regions, and a plurality of pixel units being arranged in the plurality of pixel regions, respectively; and each pixel unit of the plurality of pixel units comprising a thin-film transistor and a light-emitting device in the display region, wherein
the display substrate further comprises a plurality of fan-out traces in the display region; and each fan-out trace of the plurality of fan-out traces is, at a top of the display region, electrically connected to a data line corresponding thereto, and the plurality of fan-out traces are arranged in a different layer from the plurality of data lines and the plurality of gate lines, and the display substrate further comprises a bonding region on a first side of the display region, each fan-out trace of the plurality of fan-out traces comprises a first sub-connection line, a second sub-connection line and a third sub-connection line which are electrically connected in sequence, a first end of a first sub-connection line of each fan-out trace of the plurality of fan-out traces is directly electrically connected to a data line corresponding to the first sub-connection line through a first via at the top of the display region and in a middle region in the display region, and a second end of the first sub-connection line is connected to a first end of a second sub-connection line corresponding to the first sub-connection line; a second end of the second sub-connection line is connected to a first end of a third sub-connection line corresponding to the second sub-connection line; the respective first sub-connection lines of the plurality of fan-out traces are arranged side by side in a middle region in the display region; respective first sub-connection lines of the plurality of fan-out traces are away from the bonding region relative to respective second sub-connection lines of the plurality of fan-out traces; a spacing between two adjacent third sub-connection lines, among respective third sub-connection lines of the plurality of fan-out traces, is smaller than a spacing between two adjacent first sub-connection lines; and a direction along which the respective third sub-connection lines and/or the respective first sub-connection lines of the plurality of fan-out traces extend in the different layer from the plurality of data lines and the plurality of gate lines is identical to a direction along which the plurality of data lines extend, and the first via is arranged at a second side of the display region, and the second side and the first side of the display region are two opposite sides along a direction that the plurality of data lines extend in a layer different from the plurality of fan-out traces.

2 . The display substrate according to claim 1 , further comprising an interlayer insulation layer on a side of a layer where the plurality of data lines are situated away from the base substrate, wherein
the plurality of fan-out traces are situated on a side of the interlayer insulation layer away from the plurality of data lines; and each fan-out trace of the plurality of fan-out traces is connected to the data line corresponding to the fan-out trace through the first via penetrating through the interlayer insulation layer.

3 . The display substrate according to claim 2 , wherein the data line and a source electrode and a drain electrode of the thin-film transistor are arranged in a same layer; and
the display substrate further comprises a passivation layer, a first planarization layer and a second planarization layer successively arranged on a side of the data line away from the base substrate, and a transfer electrode arranged between the first planarization layer and the second planarization layer, wherein the transfer electrode is connected to the drain electrode of the thin-film transistor through a second via penetrating through the passivation layer and the first planarization layer; a first electrode of the light-emitting device is connected to the transfer electrode through a third via penetrating through the second planarization layer; and the fan-out trace and the transfer electrode are insulated from each other, arranged in a same layer and made of a same material.

4 . The display substrate according to claim 1 , wherein the data line and a source electrode and a drain electrode of the thin-film transistor are arranged in a same layer; and
the display substrate further comprises a passivation layer, a first planarization layer and a second planarization layer successively arranged on a side of the data line away from the base substrate, and a transfer electrode arranged between the first planarization layer and the second planarization layer, wherein the transfer electrode is connected to the drain electrode of the thin-film transistor through a second via penetrating through the passivation layer and the first planarization layer; a first electrode of the light-emitting device is connected to the transfer electrode through a third via penetrating through the second planarization layer; and the fan-out trace and the transfer electrode are insulated from each other, arranged in a same layer and made of a same material.

5 . The display substrate according to claim 1 , wherein
the light-emitting device in each pixel region comprises an organic light-emitting diode which has a first electrode, a second electrode and an organic luminescent layer between the first electrode and the second electrode; the organic light-emitting diode is situated on a side of the plurality of fan-out traces distal to the base substrate; and the direction along which the respective third sub-connection lines of the plurality of fan-out traces extend is identical to the direction along which the plurality of data lines extend, each third sub-connection line is situated on a side of a data line corresponding to the third sub-connection line distal to the base substrate and is also situated on a side of an organic luminescent layer corresponding to the third sub-connection line close to the base substrate, and an orthographic projection of the third sub-connection line on the base substrate falls within a range of an orthographic projection of an organic light-emitting diode corresponding to the third sub-connection line on the base substrate.

6 . The display substrate according to claim 5 , wherein an included angle between the second sub-connection line and the first sub-connection line and/or an included angle between the second sub-connection line and the third sub-connection line range from 80 degrees to 100 degrees.

7 . The display substrate according to claim 1 , wherein an included angle between the second sub-connection line and the first sub-connection line and/or an included angle between the second sub-connection line and the third sub-connection line range from 80 degrees to 100 degrees.

8 . The display substrate according to claim 1 , wherein the pixel unit further comprises a storage capacitor; a first plate of the storage capacitor and the gate electrode of the thin-film transistor are arranged in a same layer and made of a same material; and a second plate of the storage capacitor and the source electrode and the drain electrode of the thin-film transistor are arranged in a same layer and made of a same material.

9 . The display substrate according to claim 1 , wherein the pixel unit further comprises a storage capacitor; a

Assignees

• Boe Technology Group Co Ltd

Inventors

• Xu Pan
• Zhang Dacheng
• Lin Yicheng
• Li Yongqian

Classifications

• H10W90/00

  Package configurations · CPC title

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title