Image sensor package

Patent metadata

Field	Value
Publication number	US-12563848-B2
Application number	US-202318462398-A
Country	US
Kind code	B2
Filing date	Sep 6, 2023
Priority date	Jul 27, 2023
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

An image sensor package includes an image sensor chip having a chip body, a metal dam, and a transparent substrate having a surface. The chip body has an active surface including a photosensitive area and a non-sensitive area surrounding the photosensitive area. The metal dam is formed on the non-sensitive area of the active surface, surrounds a photosensitive layer formed on the photosensitive area at intervals, is electrically insulated from the chip body, and has a thickness. A glue dam is formed on the surface and is aligned with and is bonded to the metal dam. A thickness of the glue dam is less than the thickness of the metal dam. Accordingly, the metal dam and the glue dam are combined to form a dam structure, and the quantity of liquid glue to form the glue dam is decreased. Thus, the yield of the image sensor package is enhanced.

First claim

What is claimed is:

1 . An image sensor package comprising:
an image sensor chip having a chip body comprising an active surface, a rear surface opposite to the active surface, and a photosensitive layer formed on the active surface, wherein the active surface comprises:
a photosensitive area, wherein the photosensitive layer is located in the photosensitive area; and
a non-sensitive area surrounding the photosensitive area;
a metal dam formed on the active surface of the chip body, located on the non-sensitive area of the active surface, surrounding the photosensitive area, electrically insulated from the chip body, and has a first thickness, wherein a gap is defined between an inside surface of the metal dam and an outside surface of the photosensitive area; and a transparent substrate having:
a surface facing toward the active surface of the chip body; and
a glue dam formed on the surface and having a second thickness, wherein the glue dam is aligned with the metal dam, and the transparent substrate is bonded to the image sensor chip through the glue dam and the metal dam, wherein the second thickness is less than the first thickness.

2 . The image sensor package as claimed in claim 1 , wherein a percentage value of the second thickness to a total thickness of the first and second thickness is between 14.3% and 25%.

3 . The image sensor package as claimed in claim 2 , wherein the first thickness is 30 μm and the second thickness is between 5 μm and 10 μm.

4 . The image sensor package as claimed in claim 1 , wherein an outer side of the chip body of the image sensor package and an outer side of the metal dam are flush with an outer side of the transparent substrate and an outer side of the glue dam of the transparent substrate.

5 . The image sensor package as claimed in claim 2 , wherein an outer side of the chip body of the image sensor package and an outer side of the metal dam are flush with an outer side of the transparent substrate and an outer side of the glue dam of the transparent substrate.

6 . The image sensor package as claimed in claim 1 , wherein the image sensor chip further comprises:
a plurality of conductive vias formed through the chip body and located in the non-sensitive area; a plurality of inner metal pads formed on the active surface of the chip body and respectively connected to the conductive vias; and a wiring layer formed on the active surface of the chip body and located on the non-sensitive area of the active surface, wherein the metal dam is formed on the wiring layer to be electrically insulated from the chip body, wherein the wiring layer comprises:
a plurality of metal wires formed on the active surface of the chip body and connected to the photosensitive layer and the inner metal pads; and
an insulation layer formed on the active surface of the chip body and covering the metal wires, wherein the metal dam is formed on the insulation layer.

7 . The image sensor package as claimed in claim 2 , wherein the image sensor chip further comprises:
a plurality of conductive vias formed through the chip body and located in the non-sensitive area; a plurality of inner metal pads formed on the active surface of the chip body and respectively connected to the conductive vias; and a wiring layer formed on the active surface of the chip body and located on the non-sensitive area of the active surface, wherein the metal dam is formed on the wiring layer to be electrically insulated from the chip body, wherein the wiring layer comprises:
a plurality of metal wires formed on the active surface of the chip body and connected to the photosensitive layer and the inner metal pads; and
an insulation layer formed on the active surface of the chip body and covering the metal wires, wherein the metal dam is formed on the insulation layer.

8 . The image sensor package as claimed in claim 6 , wherein the image sensor chip further comprises:
a plurality of outer metal pads formed on the rear surface of the chip body and respectively connected to the conductive vias; and a plurality of outer connectors respectively formed on the outer metal pads.

9 . The image sensor package as claimed in claim 7 , wherein the image sensor chip further comprises:
a plurality of outer metal pads formed on the rear surface of the chip body and respectively connected to the conductive vias; and a plurality of outer connectors respectively formed on the outer metal pads.

10 . The image sensor package as claimed in claim 6 , wherein the image sensor package further comprises:
a redistribution layer formed on the rear surface of the chip body; and a plurality of outer connectors formed on the redistribution layer, wherein the redistribution layer is connected to the conductive vias and the outer connectors.

11 . The image sensor package as claimed in claim 7 , wherein the image sensor package further comprises:
a redistribution layer formed on the rear surface of the chip body; and a plurality of outer connectors formed on the redistribution layer, wherein the redistribution layer is connected to the conductive vias and the outer connectors.

12 . The image sensor package as claimed in claim 6 , wherein the insulation layer of the wiring layer comprises:
a passivation layer formed on the active surface of the chip body and covering the metal wires; and a dielectric layer formed on the passivation layer, wherein the metal dam is formed on the dielectric layer.

13 . The image sensor package as claimed in claim 7 , wherein the insulation layer of the wiring layer comprises:
a passivation layer formed on the active surface of the chip body and covering the metal wires; and a dielectric layer formed on the passivation layer, wherein the metal dam is formed on the dielectric layer.

14 . The image sensor package as claimed in claim 1 , wherein the metal dam has a light-absorbing layer formed on an exposed surface thereof.

15 . The image sensor package as claimed in claim 2 , wherein the metal dam has an exposed surface and a light-absorbing layer formed on the exposed surface.

16 . The image sensor package as claimed in claim 6 , wherein the metal dam has an exposed surface and a light-absorbing layer formed on the exposed surface.

17 . The image sensor package as claimed in claim 7 , wherein the metal dam is made by an electroless-plated metal.

18 . The image sensor package as claimed in claim 16 , wherein a melting point of the metal dam is greater than or is equal to 300° C.

19 . The image sensor package as claimed in claim 17 , where a melting point of the metal dam is greater than or is equal to 300° C.

Assignees

• Powertech Technology Inc

Inventors

• Hsu Hung-Hsin

Classifications

• H10F39/811

  Interconnections · CPC title

• H10F39/804 Primary

  Containers or encapsulations · CPC title