Solar cells having hybrid architectures including differentiated p-type and n-type regions with offset contacts

Patent metadata

Field	Value
Publication number	US-12563846-B2
Application number	US-202519030278-A
Country	US
Kind code	B2
Filing date	Jan 17, 2025
Priority date	Mar 29, 2019
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A solar cell, and methods of fabricating said solar cell, are disclosed. The solar cell can include a first emitter region over a substrate, the first emitter region having a perimeter around a portion of the substrate. A first conductive contact is electrically coupled to the first emitter region at a location outside of the perimeter of the first emitter region.

First claim

What is claimed is:

1 . A solar cell, comprising:
a first insulator layer above a substrate, the first insulator layer having a first opening, a second opening, and a third opening; a first semiconductor layer above the substrate, wherein a first portion of the first semiconductor layer is in the first, second and third openings of the first insulator layer, and a second portion of the first semiconductor layer is over a portion of the first insulator layer; a second semiconductor layer above the substrate, the second semiconductor layer between the first insulator layer and the substrate, the second semiconductor layer having a conductivity type opposite a conductivity type of the first semiconductor layer; a second insulator layer over the first semiconductor layer, the second insulator layer having a first opening over the second portion of the first semiconductor layer between the first and second openings of the first dielectric layer, and the second insulator layer having a second opening over the second portion of the first semiconductor layer between the second and third openings of the first dielectric layer; and a conductive contact in the first and second openings of the second insulator layer, in the second opening of the first insulator layer, but not in the first and third openings of the first insulator layer, the conductive contact electrically coupled to the second portion of the first semiconductor layer at first and second locations beneath the first and second openings of the second insulator layer, respectively.

2 . The solar cell of claim 1 , wherein the first portion of the first semiconductor layer is continuous with the second portion of the first semiconductor layer.

3 . The solar cell of claim 1 , wherein the first semiconductor layer comprises polycrystalline silicon, and the substrate comprises monocrystalline silicon.

4 . The solar cell of claim 3 , further comprising:
a dielectric layer between the first semiconductor layer and the substrate.

5 . The solar cell of claim 1 , wherein the conductive contact is further on a portion of the second insulator layer over the first insulator layer.

6 . The solar cell of claim 1 , wherein the second semiconductor layer has P-type conductivity, and the first semiconductor layer has N-type conductivity.

7 . The solar cell of claim 1 , wherein the second semiconductor layer has N-type conductivity, and the first semiconductor layer has P-type conductivity.

8 . The solar cell of claim 1 , wherein the first insulator layer is over a backside of the substrate.

9 . The solar cell of claim 1 , wherein the second insulator layer has a lateral width greater than a lateral width of the first semiconductor layer.

10 . The solar cell of claim 1 , wherein the conductive contact partially vertically overlaps with the first and third openings of the first insulator layer.

11 . A method of fabricating a solar cell, the method comprising:
forming a first insulator layer above a substrate, the first insulator layer having a first opening, a second opening, and a third opening; forming a first semiconductor layer above the substrate, wherein a first portion of the first semiconductor layer is in the first, second and third openings of the first insulator layer, and a second portion of the first semiconductor layer is over a portion of the first insulator layer; forming a second semiconductor layer above the substrate, the second semiconductor layer between the first insulator layer and the substrate, the second semiconductor layer having a conductivity type opposite a conductivity type of the first semiconductor layer; forming a second insulator layer over the first semiconductor layer, the second insulator layer having a first opening over the second portion of the first semiconductor layer between the first and second openings of the first dielectric layer, and the second insulator layer having a second opening over the second portion of the first semiconductor layer between the second and third openings of the first dielectric layer; and forming a conductive contact in the first and second openings of the second insulator layer, in the second opening of the first insulator layer, but not in the first and third openings of the first insulator layer, the conductive contact electrically coupled to the second portion of the first semiconductor layer at first and second locations beneath the first and second openings of the second insulator layer, respectively.

12 . The method of claim 11 , wherein the first portion of the first semiconductor layer is continuous with the second portion of the first semiconductor layer.

13 . The method of claim 11 , wherein the first semiconductor layer comprises polycrystalline silicon, and the substrate comprises monocrystalline silicon.

14 . The method of claim 13 , further comprising:
forming a dielectric layer between the first semiconductor layer and the substrate.

15 . The method of claim 11 , wherein the conductive contact is further on a portion of the second insulator layer over the first insulator layer.

16 . The method of claim 11 , wherein the second semiconductor layer has P-type conductivity, and the first semiconductor layer has N-type conductivity.

17 . The method of claim 11 , wherein the second semiconductor layer has N-type conductivity, and the first semiconductor layer has P-type conductivity.

18 . The method of claim 11 , wherein the first insulator layer is over a backside of the substrate.

19 . The method of claim 11 , wherein the second insulator layer has a lateral width greater than a lateral width of the first semiconductor layer.

20 . The method of claim 11 , wherein the conductive contact partially vertically overlaps with the first and third openings of the first insulator layer.

Assignees

• Maxeon Solar Pte Ltd

Inventors

• Smith David D
• Cotter Jeffrey El
• Barkhouse David Aaron Randolph
• Kim Taeseok

Classifications

• H10F77/219 Primary

  Arrangements for electrodes of back-contact photovoltaic cells · CPC title

• H10F71/00

  Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title

• H10F10/174

  comprising monocrystalline or polycrystalline materials · CPC title

• H10F71/121

  The active layers comprising only Group IV materials · CPC title

• H10F10/165

  the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells · CPC title