Composite gate dielectric for high-voltage device

Patent metadata

Field	Value
Publication number	US-12563812-B2
Application number	US-202318150266-A
Country	US
Kind code	B2
Filing date	Jan 5, 2023
Priority date	Oct 4, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.

First claim

What is claimed is:

1 . A method of forming an integrated chip, comprising:
forming a recess within a substrate according to a first mask; forming a first gate dielectric within the recess; forming a second gate dielectric layer on the first gate dielectric, the second gate dielectric layer continuously extending from below the first mask to over the first mask; forming a second mask on the second gate dielectric layer, the second mask continuously extending from below a top of the second gate dielectric layer to over the top of the second gate dielectric layer; performing a first etching process to expose one or more upper surfaces of the second gate dielectric layer that are between the first mask and the second mask; performing a second etching process to recess the second gate dielectric layer and to form a second gate dielectric that has a topmost surface between topmost and bottommost surfaces of the first mask and the second mask; and forming a gate electrode over the second gate dielectric after removing the first mask and the second mask.

2 . The method of claim 1 , wherein recessing the second gate dielectric layer forms one or more protrusions extending outward from a recessed upper surface of the second gate dielectric.

3 . The method of claim 1 , further comprising:
forming an upper dielectric onto the topmost surface of the second mask and within a recess in the topmost surface of the second mask; and performing a planarization process to remove a part of the upper dielectric and to expose the second mask.

4 . The method of claim 1 , wherein the first mask and the second mask are silicon nitride.

5 . The method of claim 1 , wherein the second etching process has a greater etching selectivity between the first mask and the second gate dielectric layer than the first etching process.

6 . The method of claim 1 ,
wherein the first gate dielectric is formed using a thermal oxidation process; and wherein the second gate dielectric layer is formed using a vapor deposition technique performed at a temperature of greater than approximately 400° C.

7 . A method of forming an integrated chip, comprising:
etching a substrate to form a recess within the substrate; performing an oxidation process to form a first gate dielectric along an upper surface and sidewalls of the substrate that form the recess; depositing a second gate dielectric along an upper surface and interior sidewalls of the first gate dielectric, wherein the second gate dielectric has a larger thickness at a lateral center of the second gate dielectric than along an outermost sidewall of the second gate dielectric, and wherein the second gate dielectric has a central region surrounded by a peripheral region, the central region being recessed below the peripheral region; and depositing a gate electrode material over the central region and the peripheral region of the second gate dielectric.

8 . The method of claim 7 , wherein the second gate dielectric is formed by a deposition process that is performed at a temperature of greater than approximately 500° C.

9 . The method of claim 7 ,
wherein both the central region and the peripheral region of the second gate dielectric are completely laterally confined within a footprint of the recess; and wherein the second gate dielectric vertically extends outward from the recess to above the substrate.

10 . The method of claim 7 , wherein the interior sidewalls of the first gate dielectric continuously extend between a lower surface and the upper surface of the first gate dielectric to form a recess in the upper surface of the first gate dielectric, the second gate dielectric being deposited to fill the recess.

11 . The method of claim 7 , further comprising:
depositing a sacrificial layer over the substrate; patterning the sacrificial layer to form an opening extending through the sacrificial layer; exposing the substrate to an etchant according to the opening to form the recess; and depositing the second gate dielectric along sidewalls and over an upper surface of the sacrificial layer.

12 . The method of claim 11 , further comprising:
performing a chemical mechanical polishing (CMP) process to remove a part of the second gate dielectric that is over the sacrificial layer; performing an etching process to recess the second gate dielectric after performing the CMP process; and removing the sacrificial layer after performing the etching process.

13 . The method of claim 11 , further comprising:
etching the substrate to form a plurality of fins protruding outward from an additional upper surface of the substrate; forming a dielectric material along sidewalls of the plurality of fins; and depositing the sacrificial layer to cover the plurality of fins and the dielectric material.

14 . The method of claim 13 , further comprising:
recessing the dielectric material after removing the sacrificial layer; and depositing the gate electrode material over and along the sidewalls of the plurality of fins.

15 . The method of claim 14 , wherein the gate electrode material is concurrently deposited over the central region and the peripheral region of the second gate dielectric and over and along the sidewalls of the plurality of fins.

16 . The method of claim 7 , wherein the central region of the second gate dielectric is vertically at or above a topmost surface of the first gate dielectric.

17 . A method of forming an integrated chip, comprising:
etching a substrate according to a first sacrificial mask to form a recess within the substrate; performing an oxidation process to form a first gate dielectric along an upper surface and sidewalls of the substrate that form the recess; depositing a second gate dielectric along a top surface and interior sidewalls of both the first gate dielectric and the first sacrificial mask; depositing a second sacrificial mask along a top surface and interior sidewalls of the second gate dielectric; removing upper portions of the second gate dielectric and the second sacrificial mask to expose upper surfaces of the second gate dielectric that are laterally between the first sacrificial mask and the second sacrificial mask; etching the upper surfaces of the second gate dielectric to recess the second gate dielectric below tops of the first sacrificial mask and the second sacrificial mask; removing the first sacrificial mask and the second sacrificial mask; and depositing a gate electrode material over the second gate dielectric.

18 . The method of claim 17 , wherein the first sacrificial mask and the second sacrificial mask comprise a dielectric material.

19 . The method of claim 17 , wherein the second gate dielectric vertically separates a topmost surface of the first gate dielectric from the gate electrode material.

20 . The method of claim 17 , wherein the second gate dielectric comprises protrusions extending outward from the second gate dielectric, the protrusions having a curved surface.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Song Jhu-Min
• Chen Ying-Chou
• Ciou Yi-Kai
• Chou Chien-Chih
• Chen Fei-Yun
• Jong Yu-Chang
• Lin Chi-Te

Classifications

• H10D30/60 Primary

  Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence) · CPC title

• H10D84/834

  comprising FinFETs · CPC title

• H10D84/0158

  the components including FinFETs · CPC title

• H10D84/0144

  Manufacturing their gate insulating layers · CPC title

• H10D84/038

  using silicon technology, e.g. SiGe · CPC title