Semiconductor device

Patent metadata

Field	Value
Publication number	US-12563784-B2
Application number	US-202318199133-A
Country	US
Kind code	B2
Filing date	May 18, 2023
Priority date	Jul 21, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

The present disclosure provides for semiconductor devices including field effect transistors. In some embodiments, the semiconductor device includes active structures extending in a first direction on a substrate, an isolation pattern formed in a trench between the active structures, gate structures extending in a second direction across the active structures, a cutting insulation pattern formed between end portions of the gate structures in the second direction, and a lower impurity region at an upper portion of the isolation pattern. A first shape of a lower portion of the cutting insulation pattern disposed under an uppermost surface of the isolation pattern is different from a second shape of a lower portion of the gate structures disposed under the uppermost surface of the isolation pattern. The gate structures are formed on the active structures and the isolation pattern. The lower impurity region contacts at least a portion of the cutting insulation pattern.

First claim

What is claimed is:

1 . A semiconductor device, comprising:
active structures extending in a first direction on a substrate; an isolation pattern formed in a trench between the active structures; gate structures extending in a second direction across the active structures, the gate structures being formed on the active structures and the isolation pattern, the second direction being perpendicular to the first direction; a cutting insulation pattern formed between end portions of the gate structures in the second direction; and a lower impurity region at an upper portion of the isolation pattern, the lower impurity region contacting at least a portion of the cutting insulation pattern, wherein a first shape of a lower portion of the cutting insulation pattern disposed under an uppermost surface of the isolation pattern is different from a second shape of a lower portion of the gate structures disposed under the uppermost surface of the isolation pattern, and wherein a first width in the first direction of the lower portion of the gate structures is greater than a second width in the first direction of an upper portion of the gate structures.

2 . The semiconductor device of claim 1 , wherein the second shape of the lower portion of the gate structures comprises a laterally convexly rounded shape, in a cross-sectional view in the first direction.

3 . The semiconductor device of claim 1 , wherein the lower portion of the cutting insulation pattern has a sidewall slope; and
wherein the lower portion of the cutting insulation pattern has an inner width that decreases in a downward direction.

4 . The semiconductor device of claim 1 , wherein a plurality of cutting insulation patterns are disposed on the lower impurity region.

5 . The semiconductor device of claim 1 , wherein a first level of a bottom of the gate structures disposed on the isolation pattern is lower than a second level of an uppermost surface of the lower impurity region.

6 . The semiconductor device of claim 1 , wherein a first height of a bottom of the cutting insulation pattern is different from a second height of a bottom of the gate structures disposed on the isolation pattern.

7 . The semiconductor device of claim 1 , wherein a bottom of the cutting insulation pattern is higher than a bottom of the lower impurity region.

8 . The semiconductor device of claim 1 , wherein a bottom of the cutting insulation pattern is lower than a bottom of the lower impurity region.

9 . The semiconductor device of claim 1 , wherein the lower impurity region comprises doping using at least one of silicon, carbon, and boron.

10 . The semiconductor device of claim 1 , wherein the active structures comprise semiconductor patterns spaced apart from each other in a vertical direction;
wherein the vertical direction is perpendicular to an upper surface of the substrate; and wherein the gate structures surrounds the semiconductor patterns.

11 . A semiconductor device, comprising:
lower active patterns protruding from a surface of a substrate surface, the lower active patterns extending in a first direction; a channel structure on each of the lower active patterns, the channel structure comprising semiconductor patterns spaced apart from each other in a vertical direction, the vertical direction being perpendicular to an upper surface of the lower active patterns; impurity region structures on each of the lower active patterns, the impurity region structures formed on both sidewalls of the channel structure; an isolation pattern formed in a trench between the lower active patterns; gate structures on the isolation pattern while surrounding the channel structure, the gate structures extending in a second direction, the second direction being perpendicular to the first direction; a cutting insulation pattern formed between end portions of the gate structures in the second direction; and a lower impurity region formed at an upper portion of the isolation pattern, the lower impurity region contacting at least a portion of the cutting insulation pattern, wherein a bottom of the gate structures disposed on the isolation pattern is lower than an uppermost surface of the lower impurity region, wherein a lower portion of the gate structures is disposed under an uppermost surface of the isolation pattern, and wherein a first width in the first direction of the lower portion of the gate structures is greater than a second width in the first direction of an upper portion of the gate structures.

12 . The semiconductor device of claim 11 , wherein a shape of a lower portion of the gate structures disposed under an uppermost surface of the isolation pattern comprises a laterally convexly rounded shape, in a cross-sectional view in the first direction.

13 . The semiconductor device of claim 11 , wherein a lower portion of the cutting insulation pattern disposed under an uppermost surface of the isolation pattern comprises a sidewall slope; and
wherein the lower portion of the cutting insulation pattern has an inner width that decreases in a downward direction.

14 . The semiconductor device of claim 11 , wherein a first height of a bottom of the cutting insulation pattern is different from a second height of a bottom of the gate structures disposed on the isolation pattern.

15 . The semiconductor device of claim 11 , wherein the lower impurity region comprises doping using at least one of silicon, carbon, and boron.

16 . A semiconductor device, comprising:
active structures extending in a first direction on a substrate; an isolation pattern formed in a trench between the active structures; gate structures extending in a second direction across the active structures, the gate structures being formed on the active structures and the isolation pattern, the second direction being perpendicular to the first direction; and a cutting insulation pattern formed between end portions of the gate structures in the second direction, and extending to an upper portion of the isolation pattern, wherein a first shape of a lower portion of the cutting insulation pattern disposed under the uppermost surface of the isolation pattern is different from a second shape of a lower portion of the gate structures disposed on the isolation pattern, wherein a bottom of the gate structures disposed on the isolation pattern is lower than an uppermost surface of a lower impurity region, and wherein a first width in the first direction of the lower portion of the gate structures is greater than a second width in the first direction of an upper portion of the gate structures.

17 . The semiconductor device of claim 16 , wherein the lower impurity region is formed at an upper portion of the isolation pattern; and
wherein the lower impurity region contacts at least a portion of the cutting insulation pattern.

18 . The semiconductor device of claim 16 , wherein the lower impurity region comprises doping using at least one of silicon, carbon, and boron.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jaehyun
• LEE Jonghan
• Baek Jonghoon
• Kim Taegon
• Jung Yujin

Classifications

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title

• H10D30/6735 Primary

  having gates fully surrounding the channels, e.g. gate-all-around · CPC title

• H10D84/83

  of only insulated-gate FETs [IGFET] · CPC title