Nitride-based semiconductor circuit and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-12563765-B2
Application number	US-202217767457-A
Country	US
Kind code	B2
Filing date	Jan 7, 2022
Priority date	Jan 7, 2022
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

A nitride-based semiconductor circuit including a first semiconductor substrate, a second semiconductor substrate, a nitride-based heterostructure, connectors, a first patterned conductive layer, a second patterned conductive layer, and connecting vias is provided. The second substrate is disposed on the first substrate. The first substrate has first dopants, and the second substrate has second dopants, which is different from the first dopants, and a pn junction is formed between the first substrate and the second substrate. The nitride-based heterostructure is disposed on the second substrate. The connectors are disposed on the nitride-based heterostructure. The first and second patterned conductive layers are disposed on the connectors. The connecting vias include a first interconnection and a second interconnection. The first interconnection electrically connects the first substrate to one of the connectors. The second interconnection electrically connects the second substrate to another one of the connectors.

First claim

The invention claimed is:

1 . A nitride-based semiconductor circuit comprising:
a first semiconductor substrate having first dopants; a second semiconductor substrate disposed on the first semiconductor substrate and having second dopants different from the first dopants to form a pn junction between the first semiconductor substrate and the second semiconductor substrate; a nitride-based heterostructure disposed on the second semiconductor substrate; a plurality of connectors disposed on the nitride-based heterostructure; a first patterned conductive layer disposed on the connectors; a second patterned conductive layer disposed on the connectors; and a plurality of connecting vias going through the nitride-based heterostructure, wherein the connecting vias comprise:
a first interconnection electrically connecting the first semiconductor substrate to one of the connectors or an external power source through the first patterned conductive layer; and
a second interconnection electrically connecting the second semiconductor substrate to another one of the connectors or another external power source through the second patterned conductive layer;
wherein the connectors comprise a first and second source connectors, a first and second drain connectors, and a first and second gate connectors, wherein the first source connector, the first drain connector, and the first gate connector and a part of the nitride-based heterostructure are configured to constitute a first HEMT structure, wherein the second source connector, the second drain connector, and the second gate connector and another part of the nitride-based heterostructure are configured to constitute a second HEMT structure located beside the first HEMT structure, and a threshold voltage of the second HEMT structure is higher than a threshold voltage of the first HEMT structure, and the second patterned conductive layer connects the first source connector to the second drain connector.

2 . The nitride-based semiconductor circuit of claim 1 , wherein the first interconnection electrically connects the first drain connector to the first semiconductor substrate, and the second interconnection electrically connects the second semiconductor substrate to the first source connector and the second source connector.

3 . The nitride-based semiconductor circuit of claim 1 , wherein the first semiconductor substrate has a heavily doped area, and the first interconnection is connected to the heavily doped area.

4 . The nitride-based semiconductor circuit of claim 3 , wherein the heavily doped area surrounds a projection of the first HEMT structure on the first semiconductor substrate.

5 . The nitride-based semiconductor circuit of claim 3 , wherein the heavily doped area surrounds both projections of the first and second HEMT structures on the first semiconductor substrate.

6 . The nitride-based semiconductor circuit of claim 1 , wherein the first interconnection electrically connects the second source connector to the first semiconductor substrate, and the second interconnection electrically connects the first source connector and the second source connector to the second semiconductor substrate.

7 . The nitride-based semiconductor circuit of claim 3 , wherein the heavily doped area surrounds a projection of the second HEMT structure on the first semiconductor substrate.

8 . The nitride-based semiconductor circuit of claim 1 , further comprising:
an oxide layer in contact with the second gate connector and isolated from the first gate connector; and a nitride layer in contact with the first gate connector.

9 . The nitride-based semiconductor circuit of claim 8 , wherein the second gate connector comprises:
a doped nitride-based semiconductor layer disposed on the nitride-based heterostructure and in direct contact with the oxide layer; and a gate electrode disposed on the doped nitride-based semiconductor layer.

10 . The nitride-based semiconductor circuit of claim 9 , wherein a top surface or a side surface of the gate electrode is free from coverage of the oxide layer.

11 . The nitride-based semiconductor circuit of claim 9 , wherein the gate electrode is isolated from the oxide layer.

12 . The nitride-based semiconductor circuit of claim 1 , further comprising a third semiconductor substrate, wherein the first semiconductor substrate is disposed on the third semiconductor substrate, and the second and third semiconductor substrates have the same type of dopants.

13 . The nitride-based semiconductor circuit of claim 1 , wherein the first and second semiconductor substrates form a first interface therebetween with the pn junction across the first interface.

14 . The nitride-based semiconductor circuit of claim 13 , wherein the nitride-based heterostructure comprises two nitride-based semiconductor layers having different bandgaps with a second interface formed therebetween, and the first interface is parallel with the second interface.

15 . A manufacturing method of a nitride-based semiconductor circuit comprising:
providing a first semiconductor substrate having first dopants; disposing a second semiconductor substrate having second dopants, which are different from the first dopants, on the first semiconductor substrate to form a pn junction; disposing a nitride-based heterostructure on the second semiconductor substrate; disposing a plurality of connectors on the nitride-based heterostructure; etching through part of the nitride-based heterostructure; disposing a first interconnection; disposing a first patterned conductive layer; etching through another part of the nitride-based heterostructure; disposing a second interconnection; and disposing a second patterned conductive layer on the nitride-based heterostructure, wherein the first interconnection electrically connects the first semiconductor substrate to one of the connectors or an external power source through the first patterned conductive layer, wherein the second interconnection electrically connects the second semiconductor substrate to another one of the connectors or another external power source through the second patterned conductive layer; wherein the step of disposing the connectors comprises: disposing a first gate connector and a second gate connector on the nitride-based heterostructure; disposing the oxide layer on the first and second gate connectors and the nitride-based heterostructure; etching a part of the oxide layer in contact with the first gate connector; and disposing a nitride layer on the first gate connector and the second gate connector and the oxide layer.

16 . The manufacturing method of claim 15 , wherein the step of disposing the connectors comprises:
disposing a first gate connector and a second gate connector on the nitride-based heterostructure; disposing a nitride layer on the first and second gate connectors and the nitride-based heterostructure; etching the nitride layer in contact with the second gate connector; and disposing an oxide layer on the second gate connector.

17 . The manufacturing method of claim 15 , wherein before the step of providing the first semiconductor substrate, the method comprises:
providing a third semiconductor substrate; and growing the first semiconductor substrate on the third semiconductor substrate, wherein the third and second semiconductor substrates have the same type of dopant.

18 . The manufacturing method of claim 15 , wherein after the step of providing the first semiconductor substrate, the

Assignees

• Innoscience Suzhou Technology Holding Co Ltd

Inventors

• Zhao Qiyue
• Gao Wuhao

Classifications

• H10D64/256

  for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673) · CPC title

• H10D62/8503

  Nitride Group III-V materials, e.g. AlN or GaN · CPC title

• H10D30/015

  of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT · CPC title

• H10W74/137

  the encapsulations being directly on the semiconductor body (H10W74/134 takes precedence) · CPC title

• H10W74/147

  the encapsulations being multilayered · CPC title