Transistor feedback capacitance reduction

Patent metadata

Field	Value
Publication number	US-12563758-B2
Application number	US-202318309320-A
Country	US
Kind code	B2
Filing date	Apr 28, 2023
Priority date	Apr 28, 2023
Publication date	Feb 24, 2026
Grant date	Feb 24, 2026

Abstract

The reduction of feedback capacitance in active semiconductor devices, such as the reduction in collector to base capacitance in transistors, is described. In one example, a transistor includes a substrate, an active region of the transistor in the substrate, a dielectric layer over a top surface of the substrate, and an interconnect region. The active region includes a base contact over the active region. The interconnect region includes a conductive interconnect that extends over the dielectric layer and is electrically coupled with the base contact. The interconnect region also includes a semiconductor junction region extending under the conductive interconnect in an area of the substrate outside of the active region. The addition of the semiconductor junction region under the conductive interconnect reduces the total collector to base capacitance in the transistor.

First claim

Therefore, the following is claimed:

1 . A transistor, comprising:
a substrate; an active region of the transistor in the substrate, the active region comprising a base contact over the active region; a dielectric layer over a top surface of the substrate; and an interconnect region, the interconnect region comprising:
a conductive interconnect extending over the dielectric layer and being electrically coupled with the base contact; and
a semiconductor junction region extending under the conductive interconnect in an area of the substrate outside of the active region.

2 . The transistor of claim 1 , wherein:
the conductive interconnect, the dielectric layer, and the substrate comprise a first capacitance; the semiconductor junction region under the conductive interconnect comprises a second capacitance; and the first capacitance is electrically coupled in series with the second capacitance.

3 . The transistor of claim 1 , wherein:
the conductive interconnect, the dielectric layer, and the substrate comprise a first capacitance; the semiconductor junction region under the conductive interconnect comprises a second capacitance; and the first capacitance is within 50% of the second capacitance.

4 . The transistor of claim 1 , wherein:
the conductive interconnect comprises a bond pad and an interconnect arm; and the semiconductor junction region extends under the bond pad and the interconnect arm.

5 . The transistor of claim 1 , further comprising a second dielectric layer under the conductive interconnect in an area of the substrate outside the active region.

6 . The transistor of claim 5 , wherein a thickness of the second dielectric layer is different than a thickness of the dielectric layer.

7 . The transistor of claim 5 , wherein:
the conductive interconnect, the dielectric layer, the second dielectric layer, and the substrate comprise a first capacitance; the semiconductor junction region under the conductive interconnect comprises a second capacitance; and the first capacitance is electrically coupled in series with the second capacitance.

8 . The transistor of claim 1 , further comprising a guard ring around the active region, wherein the guard ring comprises the semiconductor junction region and extends under the conductive interconnect in an area of the substrate outside of the active region.

9 . The transistor of claim 1 , further comprising a guard ring around the active region, wherein the semiconductor junction region extends under the conductive interconnect in an area of the substrate outside of the guard ring and the active region.

10 . The transistor of claim 9 , wherein the semiconductor junction region is separated from the guard ring.

11 . The transistor of claim 1 , further comprising:
a second active region of the transistor in the substrate, the second active region comprising a second base contact over the second active region; a second conductive interconnect extending over the dielectric layer and being electrically coupled with the second base contact; and a second semiconductor junction region extending under the second conductive interconnect in an area of the substrate outside of the active region and outside of the second active region.

12 . The transistor of claim 1 , wherein:
the active region further comprises an emitter contact over the active region on a top side of the substrate; and a collector contact over a bottom side of the substrate.

13 . The transistor of claim 1 , wherein:
the substrate comprises an n-type substrate; and the semiconductor junction region comprises a p-type dopant.

14 . The transistor of claim 1 , wherein:
the substrate comprises an p-type substrate; and the semiconductor junction region comprises a n-type dopant.

15 . A transistor, comprising:
a substrate; an active region of the transistor in the substrate, the active region comprising a guard ring and a base contact over the active region; a dielectric layer over a top surface of the substrate; and an interconnect region outside of the active region, the interconnect region comprising:
a conductive interconnect extending over the dielectric layer and being electrically coupled with the base contact; and
a semiconductor junction region extending under the conductive interconnect.

16 . The transistor of claim 15 , wherein:
the conductive interconnect, the dielectric layer, and the substrate comprise a first capacitance; the semiconductor junction region under the conductive interconnect comprises a second capacitance; and the first capacitance is electrically coupled in series with the second capacitance.

17 . The transistor of claim 15 , wherein:
the conductive interconnect comprises a bond pad and an interconnect arm; and the semiconductor junction region extends under the bond pad and the interconnect arm.

18 . The transistor of claim 15 , further comprising a second dielectric layer under the conductive interconnect in an area of the substrate outside the active region.

19 . The transistor of claim 15 , wherein the semiconductor junction region is separated from the guard ring.

20 . The transistor of claim 15 , wherein the semiconductor junction region is an extension of the guard ring.

Assignees

• Macom Tech Solutions Holdings Inc

Inventors

• Pal Debdas
• Kumar Parshant
• Bilotta Stephen
• Boles Timothy E

Classifications

• H10D62/106

  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions · CPC title

• H10D64/111

  Field plates · CPC title

• H10D62/115

  Dielectric isolations, e.g. air gaps · CPC title

• H10D10/80 Primary

  Heterojunction BJTs · CPC title